MAX1020_12 Datasheet, PDF (38/44 Pages) Maxim Integrated Products – 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
t_CH
t_CL
SCLK
1
2
3
4
5
t_DH
t_DS
DIN
D15
D14
t_DOE
DOUT
D15
D7
t_CSS
t_CSPWH
D13
D12
t_DOT
D14
D13
D6
D5
D11
D12
D4
CS
32
16
8
D1
D0
t_DOD
D1
D0
t_CSH
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t_S is valid from the rising edge of CS, which fol-
lows the last data bit in the software command word.
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