DS89C430 Datasheet, PDF (35/48 Pages) Dallas Semiconductor – Ultra-High-Speed Flash Microcontrollers

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Figure 13. Page Mode 1, External Data Memory Access
(PAGES = 01, Stretch = 4, CD = 10)
XTAL1
1st
Cycle
2nd
Cycle
MOVX Instruction (Page miss)
3rd
Cycle
4th
Cycle
9th
Cycle
ALE
PSEN
RD/WR
Port 0
Inst Inst Inst Inst
Data
Inst Inst
Port 2
LSB LSB LSB LSB
MOVX
Instruction
Fetch
MSB
Memory Access (Stretch = 4)
LSB
LSB LSB
ALE
MOVX Instruction (Page hit)
1st 2nd
Cycle Cycle
3rd
Cycle
4th
Cycle
5th
Cycle
PSEN
RD/WR
Port 0
Inst Inst Inst Inst
Port 2
LSB LSB LSB LSB
MOVX
Instruction
Fetch
Memory Access (Stretch = 4)
9th
Cycle
Data
Inst Inst Inst
LSB LSB LSB LSB
Interrupts
The DS89C430 provides 13 interrupt sources. All interrupts, with the exception of the power fail, are controlled by a
series combination of individual enable bits and a global enable (EA) in the interrupt-enable register (IE.7). Setting
EA to a logic 1 allows individual interrupts to be enabled. Setting EA to a logic 0 disables all interrupts regardless of
the individual interrupt-enable settings. The power-fail interrupt is controlled by its individual enable only.
The interrupt enables and priorities are functionally identical to those of the 80C52, except that the DS89C430
supports five levels of interrupt priorities instead of the original two.
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