DS89C430 Datasheet, PDF (3/48 Pages) Dallas Semiconductor – Ultra-High-Speed Flash Microcontrollers

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Specifications to -40∞C are guaranteed by design and not production tested.
All voltages are referenced to ground.
The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that VRST (min) is specified below
that point. This indicates that there is a range of voltages [(VMIN to VRST (min)] where the processor's operation is not guaranteed, but
the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper
operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset.
While the specifications for VPFW and VRST overlap, the design of the hardware makes it so this is not possible. Within the ranges
given, there is guaranteed separation between these two voltages.
Active current is measured with a 33MHz clock source driving XTAL1, VCC = RST = 5.5V. All other pins are disconnected.
Idle mode current is measured with a 33MHz clock source driving XTAL1, VCC = 5.5V, RST at ground. All other pins are
disconnected.
Stop mode is measured with XTAL and RST grounded, VCC = 5.5V. All other pins are disconnected.
RST = 5.5V. This condition mimics the operation of pins in I/O mode.
During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition
mode.
When addressing external memory.
Guaranteed by design.
Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V.
RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode.
This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at
approximately 2V.
3 of 48