DS89C430 Datasheet, PDF (21/48 Pages) Dallas Semiconductor – Ultra-High-Speed Flash Microcontrollers

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Program Memory Access
On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB) on the DS89C430,
through 7FFFh (32kB) on the DS89C440, and through FFFFh (64kB) on the DS89C450. Exceeding the maximum
address of on-chip program memory causes the device to access off-chip memory. The maximum on-chip decoded
address is selectable by software using the ROMSIZE feature. Software can cause the DS89C430 to behave like a
device with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum
memory size is dynamically variable. Thus a portion of memory can be removed from the memory map to access
off-chip memory and then be restored to access on-chip memory. In fact, all the on-chip memory can be removed
from the memory map allowing the full 64kB memory space to be addressed from off-chip memory. Program
memory addresses that are larger than the selected maximum are automatically fetched from outside the part
through ports 0 and 2. Figure 6 shows a depiction of the memory map.
The ROMSIZE register is used to select the maximum on-chip decoded address for program memory. Bits RMS2,
RMS1, and RMS0 have the following effect:
RMS2
0
0
0
0
1
1
1
1
RMS1
0
0
1
1
0
0
1
1
RMS0
0
1
0
1
0
1
0
1
Maximum On-Chip Program Memory
Address (Size/Address)
0kB
1kB/03FFh
2kB/07FFh
4kB/0FFFh
8kB/1FFFh
16kB/3FFFh (DS89C430 default)
32kB/7FFFh (DS89C440 default)
64kB/FFFFh (DS89C450 default)
The reset default condition for all devices is to their maximum on-chip program memory size. When accessing
external program memory, that amount of external memory would be inaccessible. To select a smaller effective
program memory size, software must alter bits RMS2ñRMS0. Altering these bits requires a timed-access
procedure, as explained later.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For example,
assume that a DS89C430 is executing instructions from internal program memory near the 12kB boundary
(~3000h) and that the ROMSIZE register is currently configured for a 16kB internal program space. If software
reconfigures the ROMSIZE register to 4kB (0000hñ0FFFh) in the current state, the device immediately jumps to
external program execution because program code from 4kB to 16kB (1000hñ3FFFh) is no longer located on-chip.
This could result in code misalignment and execution of an invalid instruction. The recommended method is to
modify the ROMSIZE register from a location in memory that is internal (or external) both before and after the
operation. In the above example, the instruction that modifies the ROMSIZE register should be located below the
4kB (1000h) boundary or above the 16kB (3FFFh) boundary so that it is unaffected by the memory modification.
The same precaution should be applied if the internal program memory size is modified while executing from
external program memory.
For nonpage mode operations, off-chip memory is accessed using the multiplexed address/data bus on P0 and the
MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the
standard 8051 method of expanding on-chip memory. Off-chip program memory access also occurs if the EA pin is
a logic 0. EA overrides all ROMSIZE bit settings. The PSEN signal goes active (low) to serve as a chip enable or
output enable when ports 0 and 2 fetch from external program memory.
The RD and WR signals are used to control the external data memory device. Data memory is accessed by MOVX
instructions. The MOVX@Ri instruction uses the value in the designated working register to provide the LSB of the
address, while port 2 supplies the address MSB. The MOVX@DPTR instruction uses one of the two data pointers
to move data over the entire 64kB external data memory space. Software selects the data pointer used by writing
to the SEL bit (DPS.0).
The DS89C430 also provides a user option for high-speed external memory access by reconfiguring the external
memory interface into page mode operation.
Note: When using the original 8051 expanded bus structure, the throughput is reduced by 75% compared with that
of internal operations. This is because of the CPU being stalled for three out of four clocks, waiting for the data
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