MAX1549ETL Datasheet, PDF (33/35 Pages) Maxim Integrated Products – Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output

Dual, Interleaved, Fixed-Frequency Step-Down
Controller with a Dynamically Adjustable Output
VOLTAGE POSITIONING THE OUTPUT
1.4V
A
ESR VOLTAGE STEP
(I_STEP x R_ESR)
CAPACITIVE SOAR
(dV/dt = I_OUT / C_OUT)
V_OUT
1.4V
B
CAPACITIVE SAG
(dV/dt = I_OUT / C_OUT)
RECOVERY
A. CONVENTIONAL CONVERTER (50mV/div)
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
I_LOAD
Figure 11. Voltage-Positioning Transient Response
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Since the out-
put voltage is lower under load, the processor draws less
current. The result is lower power dissipation in the
processor, although extra power is dissipated in the cur-
rent-sense element. However, the current-sense element
used for current-limit protection can also be used for
voltage positioning, further reducing the overall power
dissipation. In effect, the processor’s power dissipation
is saved and the power supply dissipates some of the
savings, but both the net savings and the transfer of dis-
sipation away from the hot processor are beneficial.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low switch-
ing losses and clean, stable operation. The switching
power stage requires particular attention (Figure 12). If
possible, mount all the power components on the top
side of the board, with their ground terminals flush
against one another. Refer to the MAX1549 evaluation kit
data sheet for a specific layout example. Follow these
guidelines for good PC board layout:
• Use a star-ground connection on the power ground
plane to minimize the crosstalk between OUT1 and
OUT2.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
• When tradeoffs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Minimize current-sensing errors by connecting
CSH_ and CSL_ directly across the current-sense
resistor (R_{SENSE_}).
• Route all high-speed switching nodes (BST_, LX_,
DH_, and DL_) away from sensitive analog areas
(REF, FB_, CSH_, and CSL_).
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (N_{L_} source, C_IN, C_{OUT_}, and D_{L_}
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N_{L_}
and N_{H_} to keep LX_, DH_, and the DL_ gate-drive
lines short and wide. The DL_ and DH_ gate traces
must be short and wide (50 mils to 100 mils wide if
the MOSFET is 1in from the controller IC) to keep
the driver impedance low and for proper adaptive
dead-time sensing.
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