MAX1549ETL Datasheet, PDF (32/35 Pages) Maxim Integrated Products – Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output

Dual, Interleaved, Fixed-Frequency Step-Down
Controller with a Dynamically Adjustable Output
Active Bus Termination (OUT1)
Active-bus-termination power supplies generate a voltage
rail that tracks a set reference. They are required to
source and sink current. DDR memory architecture
requires active bus termination. In DDR memory architec-
ture, the termination voltage is set at exactly 1/2 the mem-
ory supply voltage. Configure the main MAX1549
controller (OUT1) to generate the termination voltage
using a resistive voltage-divider at REFIN. In such an
application, OUT1 must be kept in PWM mode (SKIP =
V_CC or open) for it to source and sink current. Figure 9
shows OUT1 configured as a DDR termination regulator.
Connect GATE and FBLANK to GND when unused.
Voltage Positioning
Powering new mobile processors (CPU or GPU)
requires careful attention to detail to reduce cost, size,
and power dissipation. As processors consume more
power, it was recognized that even the fastest DC-DC
converters were inadequate to handle the severe tran-
sient power requirements. After a load transient, the
output instantly changes by ESR_COUT x ∆I_LOAD.
Conventional DC-DC converters respond by regulating
the output voltage back to its nominal state after the
load transient occurs (Figure 11), but the processor
only requires that the output voltage remains above a
specified minimum value. Dynamically positioning the
output voltage to this lower limit allows the use of fewer
output capacitors and reduces the power consumption
under load.
Figure 10 shows the connection of OUT_ and FB_ in volt-
age-positioned and nonvoltage-positioned circuits. In
nonvoltage-positioned circuits, the MAX1549 regulates
the voltage across the output capacitor. In voltage-posi-
tioned circuits, the MAX1549 regulates the voltage on the
inductor side of the current-sense resistor. The voltage-
positioned output voltage is reduced to:
V_OUT(VPS) = V_{OUT(NO LOAD)} - R_SENSEI_LOAD
For a conventional (nonvoltage-positioned) circuit, the
peak-to-peak voltage change is:
∆V_OUT(CONV) = 2 x (ESR_COUT x ∆I_LOAD) + V_SAG
+ V_SOAR
where V_SAG and V_SOAR are defined in Figure 11.
Setting the converter to regulate at a lower voltage
when under load allows a larger voltage step when the
output current suddenly decreases. Therefore, the
peak-to-peak voltage change for a voltage-positioned
circuit is:
∆V_OUT(VPS) = (ESR_COUT x ∆I_LOAD) + V_SAG + V_SOAR
where V_SAG and V_SOAR are defined in the Design
Procedure section. Since the amplitudes are the same
for both circuits (∆V_OUT(CONV) = ∆V_OUT(VPS)), the volt-
age-positioned circuit tolerates twice the ESR. Since
the ESR specification is achieved by paralleling several
capacitors, fewer units are needed for the voltage-posi-
tioned circuit.
R1
V_CC
C1
C2
V_DD
D_BST
V+
BST
DH
MAX1549 _LX
DL
N_H
C_BST
N_L
GND
+5V BIAS
SUPPLY
C_IN
L1
INPUT (V_IN)
REGULATED VOLTAGE
R_SENSE
VOLTAGE-POSITIONED
OUTPUT (V_OUT(VPS))
D_L
C_OUT
CSH
OUT
FB
CSL
V_OUT(VPS) = V_{OUT(NO LOAD)} - R_SENSE x I_OUT
Figure 10. Voltage-Positioned Applications Circuit
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