MAX1549ETL Datasheet, PDF(23/35 Page) Maxim Integrated Products – Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MAX1549ETL Datasheet, PDF (23/35 Pages) Maxim Integrated Products – Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output

◁

Dual, Interleaved, Fixed-Frequency Step-Down

Controller with a Dynamically Adjustable Output

Alternately, the secondary output voltage (OUT2) can

be adjusted from 0.5V to 2.7V using a resistive voltage-

divider. The MAX1549 regulates FB2 to a fixed 0.5V ref-

erence voltage, so the secondary output voltage can

be determined with the following equation:

VOUT2

VFB2 ââ1 +

â â

where VFB2 = 0.5V, RA is the resistor from the output to

FB2, and RB is the resistor from FB2 to analog ground.

Current-Limit Protection (ILIM_)

The current-limit circuit uses differential current-sense

inputs (CSH_ and CSL_) to limit the peak inductor cur-

rent. If the magnitude of the current-sense signal

exceeds the current-limit threshold, the PWM controller

turns off the high-side MOSFET (Figure 3). At the next

rising edge of the internal oscillator, the PWM controller

does not initiate a new cycle unless the current-sense

signal drops below the peak current-limit threshold. The

actual maximum load current is less than the peak cur-

rent-limit threshold by an amount equal to 1/2 the

inductor ripple current. Therefore, the maximum load

capability is a function of the current-limit threshold,

current-sense resistance, inductor value, switching fre-

quency, and duty cycle (VOUT / VIN).

Connect ILIM_ to VCC for the 70mV default threshold, or

adjust the current-limit threshold with an external resistor-

divider at ILIM_. Use a 2ÂµA to 20ÂµA divider current for

accuracy and noise immunity. The current-limit threshold

adjustment range is from 50mV to 200mV. In the

adjustable mode, the current-limit threshold voltage

equals precisely 1/10th the voltage seen at ILIM_ (VLIMIT

= 0.1VILIM_). The logic threshold for switchover to the

70mV default value is approximately VCC - 1V.

Carefully observe the PC board layout guidelines to

ensure noise and DC errors do not corrupt the differen-

tial current-sense signals seen by CSH_ and CSL_.

Place the IC close to the sense resistor with short,

direct traces, making a Kelvin-sense connection to the

current-sense resistor.

MOSFET Gate Drivers (DH_, DL_)

The DH_ and DL_ drivers are optimized for driving mod-

erately sized, high-side and larger, low-side power

MOSFETs. This is consistent with the low duty factor seen

in notebook applications, where a large VIN - VOUT differ-

ential exists. An adaptive dead-time circuit monitors the

DL_ output and prevents the high-side MOSFET from

turning on until DL_ is fully off. A similar adaptive dead-

time circuit monitors the DH_ output to prevent the low-

side MOSFET from turning on until DH_ is fully off. There

must be a low-resistance, low-inductance path from the

DL_ and DH_ drivers to the MOSFET gates for the adap-

tive dead-time circuits to work properly. Otherwise, the

MAX1549 interprets the MOSFET gates as âoffâ while

charge actually remains on the gate. Use very short, wide

traces (50 mils to 100 mils wide if the MOSFET is 1in from

the driver).

The internal pulldown transistor that drives DL_ low is

robust, with a 0.5â¦ (typ) on-resistance. This helps prevent

DL_ from being pulled up due to capacitive coupling from

the drain to the gate of the low-side MOSFETs when the

inductor node (LX_) quickly switches from ground to VIN.

Applications with high input voltages and long, inductive

driver traces may require additional gate-to-source

capacitance to ensure fast-rising LX_ edges do not pull

up the low-side MOSFETsâ gate voltage, causing shoot-

through currents. The capacitive coupling between LX_

and DL_ created by the MOSFETsâ gate-to-drain capaci-

tance (CRSS), gate-to-source capacitance (CISS - CRSS),

and additional board parasitics should not exceed the fol-

lowing minimum threshold:

VGS(TH)

VIN

â CRSS â

ââ CISS â â

Lot-to-lot variation of the threshold voltage can cause

problems in marginal designs. Typically, adding a

4700pF between DL_ and power ground (CNL in Figure

6), close to the low-side MOSFETs, greatly reduces the

voltage coupling. Do not exceed 22nF of total gate

capacitance to prevent excessive turn-off delays.

Alternately, shoot-through currents can be caused by a

combination of fast high-side MOSFETs and slow low-

side MOSFETs. If the turn-off delay time of the low-side

MOSFET is too long, the high-side MOSFETs turn on

before the low-side MOSFETs have actually turned off.

Adding a resistor less than 10â¦ in series with BST_

slows down the high-side MOSFET turn-on time, elimi-

nating the shoot-through currents without degrading

the turn-off time (Figure 6). Slowing down the high-side

MOSFET also reduces the LX_ node rise time, thereby

reducing the EMI and high-frequency coupling respon-

sible for switching noise.

Power-Up Sequence

Power-on reset (POR) occurs when VCC rises above

approximately 2V, resetting the fault latch and soft-start

counter, powering up the reference, and preparing the

PWM controllers for operation. Until VCC reaches 4.25V

(typ), the VCC undervoltage-lockout (UVLO) circuitry

inhibits switching. The controller inhibits switching by

pulling DH_ low and forcing DL_ high. When VCC rises

above 4.25V and ON_ is driven high, the activated con-

troller initializes soft-start and starts switching.

______________________________________________________________________________________ 23

▷