DS26518 Datasheet, PDF (31/312 Pages) Maxim Integrated Products – 8-Port T1/E1/J1 Transceiver

DS26518 8-Port T1/E1/J1 Transceiver
9.2 Clock Structure
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1
and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.
9.2.1 Backplane Clock Generation
The DS26518 provides facility for provision of BPCLK1 at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see
Figure 9-9). The Global Transceiver Clock Control Register 1 (GTCCR1) is used to control the backplane clock
generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can be an output
sourcing MCLKT1 or MCLKE1 as shown in Figure 9-9.
This backplane clock and frame pulse (TSSYNCIOn) can be used by the DS26518 and other IBO-equipped
devices as an “IBO Bus Master.” Hence, the DS26518 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz
clock. This can be used by the link layer devices and frames connected to the IBO bus.
Figure 9-9. Backplane Clock Generation
BPREFSEL3:0
MCLK
Pre
Scaler
PLL
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
MCLKT1
MCLKE1
BPCLK1:0
BFREQSEL
CLK
GEN
BPCLK
REFCLKIO
REFCLKIO
TSSYNCIO
The reference clock for the backplane clock generator can be as follows:
• External Master Clock. A prescaler can be used to generate T1 or E1 frequency.
• External Reference Clock REFCLKIO. This allows for multiple DS26518s to use the backplane clock from
a common reference.
• Internal LIU recovered RCLKs 1 to 8.
• The clock generator can be used to generate BPCLK1 of 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz
for the IBO.
• If MCLK or RCLKn is used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz
clock for external use.
31 of 312