DS26518 Datasheet, PDF (209/312 Pages) Maxim Integrated Products – 8-Port T1/E1/J1 Transceiver

DS26518 8-Port T1/E1/J1 Transceiver
Register Name:
Register Description:
Register Address:
TCICE1, TCICE2, TCICE3, TCICE4
Transmit Channel Idle Code Enable Registers 1 to 4
150h, 151h, 152h, 153h + (200h x (n - 1)) : where n = 1 to 8
Bit #
Name
(MSB)
7
CH8
CH16
CH24
CH32
6
CH7
CH15
CH23
CH31
5
CH6
CH14
CH22
CH30
4
CH5
CH13
CH21
CH29
3
CH4
CH12
CH20
CH28
2
CH3
CH11
CH19
CH27
1
CH2
CH10
CH18
CH26
(LSB)
0
CH1
CH9
CH17
CH25
TCICE1
TCICE2
TCICE3
TCICE4 (E1
Mode Only)
The Transmit Channel Idle Code Enable Registers (TCICE1–4) are used to determine which of the 24 T1 channels
(or 32 E1 channels) from the backplane should be overwritten with the code placed in the Transmit Idle Code
Definition Register (TIDR1–32).
Bits 7 to 0: Transmit Channels 1 to 32 Code Insertion Control Bits (CH[1:32])
0 = Do not insert data from the Idle Code Array into the transmit data stream.
1 = Insert data from the Idle Code Array into the transmit data stream.
Register Name:
Register Description:
Register Address:
TJBE1, TJBE2, TJBE3, TJBE4
Transmit Jammed Bit Eight Stuffing Registers 1 to 4
104h, 105h, 106h, 107h + (200h x (n - 1)) : where n = 1 to 8
Bit #
Name
(MSB)
7
CH8
CH16
CH24
CH32
6
CH7
CH15
CH23
CH31
5
CH6
CH14
CH22
CH30
4
CH5
CH13
CH21
CH29
3
CH4
CH12
CH20
CH28
2
CH3
CH11
CH19
CH27
1
CH2
CH10
CH18
CH26
(LSB)
0
CH1
CH9
CH17
CH25
TJBE1
TJBE2
TJBE3
TJBE4
The Transmit Jammed Bit Eight Stuffing Registers (TJBE1–4) select which of the 24 T1 channels (or 32 E1
Channels) to insert jammed bit eight stuffing. These registers are enabled by TCR4.TJBEN.
Bits 7 to 0: Transmit Channels 1 to 32 Jammed Bit Eight Stuffing Control Bits (CH[1:32])
0 = Do not affect data in this channel.
1 = Replace the channel with TJBES if the channel is all zeros.
Register Name:
Register Description:
Register Address:
TDDS1, TDDS2, TDDS3
Transmit DDS Zero Code Registers 1 to 3
108h, 109h, 10Ah + (200h x (n - 1)) : where n = 1 to 8
(MSB)
CH8
CH16
CH24
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
(LSB)
CH1
CH9
CH17
TDDS1
TDDS2
TDDS3
The Transmit DDS Zero Code Registers (TDDS1–3) select which of the 24 T1 channels to insert DDS zero code
stuffing. These registers are enabled by T1.TCR2.TDDSEN.
Bits 7 to 0: Transmit Channels 1 to 24 DDS Zero Code Control Bits (CH[1:32])
0 = Do not affect data in this channel.
1 = Replace the channel with DDS Zero Code stuffing if the channel is all zeros.
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