DS26518 Datasheet, PDF (128/312 Pages) Maxim Integrated Products – 8-Port T1/E1/J1 Transceiver

DS26518 8-Port T1/E1/J1 Transceiver
10.3 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, IBO configuration, MCLK configuration, and BPCLK1 configuration. The global registers bit
descriptions are presented below.
Table 10-12. Global Register Set
ADDRESS
NAME
DESCRIPTION
R/W
00F0h
GTCR1
Global Transceiver Control Register 1
R/W
00F1h
GFCR1
Global Framer Control Register 1
R/W
00F2h
GTCR3
Global Transceiver Control Register 3
R/W
00F3h
GTCCR1
Global Transceiver Clock Control Register 1
R/W
00F4h
GTCCR3
Global Transceiver Clock Control Register 3
R/W
00F5h
GHISR
Global HDLC-256 Interrupt Status Register
R
00F6h
GSRR1
Global Software Reset Register 1
R/W
00F7h
GHIMR
Global HDLC-256 Interrupt Mask Register
R/W
00F8h
IDR
Device Identification Register
R
00F9h
GFISR1
Global Framer Interrupt Status Register 1
R
00FAh
GBISR1
Global BERT Interrupt Status Register 1
R
00FBh
GLISR1
Global LIU Interrupt Status Register 1
R
00FCh
GFIMR1
Global Framers Interrupt Mask Register 1
R/W
00FDh
GBIMR1
Global BERT Interrupt Mask Register 1
R/W
00FEh
GLIMR1
Global LIU Interrupt Mask Register 1
R/W
Note 1:
Note 2:
Reserved registers should only be written with all zeros.
The global registers are located in the framer address space. The corresponding address space for the other seven framers is
“Reserved” and should be initialized with all zeros for proper operation.
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