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| MAX11335 Datasheet, PDF (3/37 Pages) Maxim Integrated Products – 500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs | |||
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MAX11335âMAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11335/MAX11336/MAX11337) (continued)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 500ksps, fSCLK = 8MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Crosstalk
-0.5dB below full-scale of 99.2432kHz
sine wave input to the channel being
sampled, apply full-scale 69.2139kHz
-88
dB
sine wave signal to all 15 nonselected
input channels.
CONVERSION RATE
Power-Up Time
Acquisition Time
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
tPU
tACQ
tCONV
fSCLK
Input Voltage Range
VINA
Absolute Input Voltage Range
Static Input Leakage Current
IILA
Input Capacitance
CAIN
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
VREF-
VREF+
REF+ Input Current
IREF+
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
Input Voltage Low
VIL
Conversion cycle, external clock
Internally clocked (Note 8)
Externally clocked, fSCLK = 8MHz,
16 cycles (Note 8)
RMS
Unipolar, (single ended and pseudo-
differential)
Bipolar
(Note 9)
Range bit set to 0
Range bit set to 1
AIN+, AIN- relative to GND
VAIN = VDD, GND
During acquisition time;
RANGE bit = 0 (Note 10)
During acquisition time;
RANGE bit = 1 (Note 10)
VREF+ = 2.5V, fSAMPLE = 500ksps
VREF+ = 2.5V, fSAMPLE = 0Msps
Input Voltage High
VIH
Input Hysteresis
VHYST
312
5.9
2000
0.16
8
30
2
Cycles
ns
µs
ns
8
MHz
ns
ps
0
VREF+
-VREF+/2
VREF+/2
V
-VREF+
VREF+
-0.1
VREF+ + 0.1
V
-0.1 Q1.5
FA
15
pF
7.5
-0.3
+1
V
1
VDD + 50mV V
36.7
FA
0.1
VOVDD
O 0.25
V
VOVDD
O 0.75
V
VOVDD
O 0.15
mV
Maxim Integrated
ââ3
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