MAX11335 Datasheet, PDF (25/37 Pages) Maxim Integrated Products – 500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs

MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Register Descriptions
The MAX11335–MAX11340 communicate between the
internal registers and the external circuitry through the
SPI-/QSPI-compatible serial interface. Table 1 details the
register access and control. Table 2 through Table 14
detail the various functions and configurations.
For ADC mode control, set bit 15 of the register code
identification to zero. The ADC Mode Control register
determines when and under what scan condition the
ADC operates.
To set the ADC data configuration, set the bit 15 of the
register code identification to one.
Power-Down Mode
The MAX11335–MAX11340 feature three power-down
modes.
Static Shutdown
The devices shut down when the SPM bits in the ADC
Configuration register are asserted (Table 6). There are
two shutdown options:
U Full shutdown where all circuitry is shutdown.
U Partial shutdown where all circuitry is powered down
except for the internal bias generator.
AutoShutdown with External Clock Mode
When the PM_ bits in the ADC Mode Control register are
asserted (Table 5), the device shuts down at the rising
edge of CS in the next frame. The device powers up
again at the following falling edge of CS. There are two
available options:
U AutoShutdown where all circuitry is shutdown.
U AutoStandby where all circuitry are powered down
except for the internal bias generator.
AutoShutdown with Internal Clock Mode
The device shuts down after all conversions are complet-
ed. The device powers up again at the next falling edge
of CNVST or at the rising edge of CS after the SWCNV
bit is asserted.
Table 5. Power Management Modes
PM1
0
0
PM0
0
1
MODE
Normal
AutoShutdown
FUNCTION
All circuitry is fully powered up at all times.
The device enters full shutdown mode at the end of each conversion. All circuitry
is powered down. The device powers up following the falling edge of CS. It takes 2
cycles before valid conversions take place. The information in the registers is retained.
The device powers down all circuitry except for the internal bias generator. The part
1
0
AutoStandby powers up following the falling edge of CS. It takes 2 cycles before valid conversions
take place. The information in the registers is retained.
1
1
—
Unused.
Table 6. ADC Configuration Register
BIT NAME
CONFIG_SETUP
BIT
15:11
DEFAULT
STATE
N/A
FUNCTION
Set to 10000 to select the ADC Configuration register.
REFSEL
AVGON
REFSEL VOLTAGE REFERENCE
REF- CONFIGURATION
10
0
0
External single-ended
AIN15 (for the 16-channel devices)
1
External differential
REF-
9
0
Set to 1 to turn averaging on. Valid for internal clock mode only.
Set to 0 to turn averaging off.
Maxim Integrated
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