MAX14500 Datasheet, PDF (28/41 Pages) Maxim Integrated Products – Hi-Speed USB-to-SD Card Readers with Bypass

Hi-Speed USB-to-SD Card
Readers with Bypass
SDA
SCL
Figure 14. Bit Transfer
DATA LINE STABLE;
DATA VALID
START
CONDITION
SCL
1
CHANGE OF DATA
ALLOWED
2
CLOCK PULSE FOR
ACKNOWLEDGE
8
9
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 15. Acknowledge
SDA
1
1
1
0
0
0
ADD
R/W
ACK
MSB
LSB
SCL
Figure 16. Slave Address
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 14). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 15),
which the recipient uses to handshake receipt of each
byte of data. Each byte transferred effectively requires
nine bits. The master generates the 9th clock pulse,
and the recipient pulls down SDA during the acknow-
ledge clock pulse. The SDA line is stable low during the
high period of the clock pulse. When the master is
transmitting to the MAX14500–MAX14503, the
MAX14500–MAX14503 generate the acknowledge bit
because the MAX14500–MAX14503 are the recipients.
When the MAX14500–MAX14503 are transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Addresses
The MAX14500–MAX14503 have a 7-bit long slave
address. The bit following the 7-bit slave address is the
R/W bit, which is low for a write command and high for
a read command. The address bit ADD is externally
driven high or low by the ADD input to select between
two slave addresses to avoid conflict with other I²C
addresses (Figure 16). Table 4 shows the binary values
for reads and writes.
Table 4. Slave Addresses
ADD FUNCTION
DEVICE ADDRESS
High
High
GND
GND
Read
Write
Read
Write
11100011
11100010
11100001
11100000
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