MAX14500 Datasheet, PDF (24/41 Pages) Maxim Integrated Products – Hi-Speed USB-to-SD Card Readers with Bypass

Hi-Speed USB-to-SD Card
Readers with Bypass
Table 2. Control Register (0x00)
BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT
[7:5] RESERVED
000 Set these bits to 0.
000
SD PORT 2 ANALOG SWITCHES
Analog switches are open,
SD Port 2 is a set of six analog switches connecting the SD port to the
0 disconnecting the SD port
4
SD card. This set contains: clock (CCLK2), command (CCMD2), and
four data lines (CDAT2_[3:0]). The card-present line is not available
from the SD card.
Analog switches are
1
for this port. This setting is ignored when Card Reader mode is
1 closed, connecting the SD
enabled for this port.
port to the SD card.
SD PORT 1 ANALOG SWITCHES
Analog switches are open,
SD Port 1 is a set of seven analog switches connecting the SD port to
0 disconnecting the SD port
3 ^{the SD card. This set contains: card-present (CCRD_PRST), clock}
from the SD card.
1
(CCLK1), command (CCMD1), and four data lines (CDAT1_[3:0]). The
Analog switches are
difference between Port 1 and Port 2 is the card-present line. This
1 closed, connecting the SD
setting is ignored when Card Reader mode is enabled for this port.
port to the SD card.
00, 11 ^{Card Reader mode not}
active.
CARD READER MODE
[2:1] Changing these bits in Sleep mode does not execute the action until
the host µP wakes up the MAX14500–MAX14503.
01
Card Reader mode active:
Connects to SD card 1.
00
10
Card Reader mode active:
Connects to SD card 2.
WAKEUP
In Sleep mode, the MAX14500–MAX14503 are in Pass Thru mode. SD
0
port switches are controlled by their respective bits. Entering Sleep
mode reduces the supply current by turning off the internal logic.
0
Request internal logic to
shut down.
0
Request to shut down may be delayed due to USB and de-
enumeration.
1 Wake up internal logic.
grammed to stay asserted until the status register is
read, or stay asserted for 10ms. If INT is programmed to
stay asserted, a read to the status register is required to
clear INT. INT can be programmed to be active-high or
active-low when I2C_SEL is high (I²C control). INT is
high impedance in Sleep mode (WAKEUP = 0), regard-
less of the INT polarity programmed in the I²C registers.
Use a pullup or pulldown resistor for the desired inactive
INT polarity state during Sleep mode.
Interrupt Masking
All interrupts are masked at power-up. While masked
interrupts do not assert the INT output, they do register
as changes in the interrupt request registers (IRQ1 and
IRQ2). The status register (STATUS1 = 0x12) indicates
the current state of the interrupt bits. If interrupts are
masked, polling IRQ1 and IRQ2 indicate the fields with
changes, and STATUS1 gives the current state.
Reading the IRQ registers resets the interrupt request
bits. If polling is used to read the device status, it is
required to read both the status register and the inter-
rupt request registers to check for state changes.
USB Interrupts
When enabled, the INT output asserts an interrupt for
changes in the USB connection and if the operating
system suspends the USB connection. VBUS is detect-
ed at the KVBUS input and changes in VBUS voltage
can assert an interrupt when enabled.
Power-Supply Interrupts
The MAX14500–MAX14503 feature many advanced
power-saving modes. V_CC, V_SD, and V_TM do not need to
be applied for I²C communication. Changes in V_SD and
V_TM can assert an interrupt when enabled to indicate dif-
ferent power-saving modes (see the Power-Supply
Modes section).
Busy Interrupt
When enabled, changes in the BSY bit can assert an
interrupt (see the Busy Indication (BSY) section).
SD Status Interrupt
When enabled, the SDSTAT bit asserts an interrupt for
card detection and removal upon entering Card Reader
mode for the SD card socket configured as the card
reader. The SDSTAT bit is not active during Pass Thru
mode and does not change states in the IRQ registers
upon card insertion and removal during Pass Thru mode.
24 ______________________________________________________________________________________