MAX1533 Datasheet, PDF (26/38 Pages) Maxim Integrated Products – High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers

High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
high. This turns on the synchronous-rectifier MOSFETs
with 100% duty, rapidly discharging the output capaci-
tors and clamping both outputs to ground. However,
immediately latching DL_ high typically causes slightly
negative output voltages due to the energy stored in
the output LC at the instant the OVP occurs. If the load
cannot tolerate a negative voltage, place a power
Schottky diode across the output to act as a reverse-
polarity clamp. If the condition that caused the overvolt-
age persists (such as a shorted high-side MOSFET),
the battery fuse blows. Cycle V_CC below 1V or toggle
either ON3, ON5, or SHDN to clear the fault latch and
restart the SMPS controllers.
Connect OVP to V_CC to disable the output overvoltage
protection.
Output Undervoltage Protection (UVP)
Each SMPS controller includes an output UVP protec-
tion circuit that begins to monitor the output 6144 clock
cycles (1 / f_OSC) after that output is enabled (ON_
pulled high). If either SMPS output voltage drops below
70% of its nominal regulation voltage and the UVP pro-
tection is enabled (UVP = GND), the UVP circuit sets
the fault latch, pulls PGOOD low, and shuts down both
controllers using discharge mode (see the Output
Discharge (Soft-Shutdown) section). When an SMPS
output voltage drops to 0.3V, its synchronous rectifier
turns on, clamping the discharged output to GND.
Cycle V_CC below 1V or toggle either ON3, ON5, or
SHDN to clear the fault latch and restart the SMPS
controllers.
Connect UVP to V_CC to disable the output undervoltage
protection.
Table 5. Operating Modes Truth Table
MODE
CONDITION
COMMENT
Power-Up
LDO5 < UVLO threshold.
Run
Output Overvoltage
Protection (OVP)
SHDN = high, ON3 or ON5 enabled.
Either output > 111% of nominal level,
OVP = low.
Transitions to discharge mode after V_IN POR and after REF
becomes valid. LDO5, LDO3, REF remain active. DL_ is active
if OVP is low.
Normal operation.
Exited by POR or cycling SHDN, ON3, or ON5.
Output Undervoltage
Protection (UVP)
Either output < 70% of nominal level, UVP
is enabled 6144 clock cycles (1 / f_OSC)
after the output is enabled and UVP = low.
Exited by POR or cycling SHDN, ON3, or ON5. If OVP is not
high, DL3 and DL5 go high after discharge.
Discharge
OVP is low and either SMPS output is still
high in either standby mode or shutdown
mode.
Discharge switch (10Ω) connects CSL_ to PGND. This is a
temporary state entered when LDO5 is undervoltage or on the
way to output UVLO, standby, shutdown, or thermal-shutdown
states. One SMPS can be in discharge mode while the other is
in run mode. If both outputs are discharged to 0.3V (on CSL_),
discharge mode transitions to the appropriate state.
Standby
Shutdown
ON5 and ON3 < startup threshold,
SHDN = high.
SHDN = low.
Thermal Shutdown T_J > +160°C.
Switchover Fault
Excessive current on LDO3 or LDO5
switchover transistors.
DL_ stays high if OVP is low. LDO3, LDO5 active.
All circuitry off.
Exited by POR or cycling SHDN, ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
Exited by POR or cycling SHDN, ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
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