MAX1533 Datasheet, PDF (18/38 Pages) Maxim Integrated Products – High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers

High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
SMPS to LDO Bootstrap Switchover
When the 5V main output voltage is above the LDO5
bootstrap-switchover threshold, an internal 0.75Ω (typ)
p-channel MOSFET shorts CSL5 to LDO5 while simulta-
neously shutting down the LDO5 linear regulator.
Similarly, when the 3.3V main output voltage is above
the LDO3 bootstrap-switchover threshold, an internal
1Ω (typ) p-channel MOSFET shorts CSL3 to LDO3 while
simultaneously shutting down the LDO3 linear regula-
tor. These actions bootstrap the device, powering the
internal circuitry and external loads from the output
SMPS voltages, rather than through linear regulators
from the battery. Bootstrapping reduces power dissipa-
tion due to gate charge and quiescent losses by pro-
viding power from a 90%-efficient switch-mode source,
rather than from a much-less-efficient linear regulator.
The output current limit increases to 200mA when the
LDO_ outputs are switched over.
SMPS 5V Bias Supply (LDO5 and V_CC)
The A switch-mode power supplies (SMPS) require a
5V bias supply in addition to the high-power input sup-
ply (battery or AC adapter). This 5V bias supply is gen-
erated by the MAX1533/MAX1537s’ internal 5V linear
regulator (LDO5). This bootstrapped LDO allows the
MAX1533/MAX1537 to power-up independently. The
gate-driver input supply is connected to the fixed 5V
linear-regulator output (LDO5). Therefore, the 5V LDO
supply must provide V_CC (PWM controller) and the
gate-drive power, so the maximum supply current
required is:
I_BIAS = I_CC + f_SW (Q_G(LOW) + Q_G(HIGH))
= 5mA to 50mA (typ)
where I_CC is 1mA (typ), f_SW is the switching frequency,
and Q_G(LOW) and Q_G(HIGH) are the MOSFET data
sheet’s total gate-charge specification limits at V_GS = 5V.
Reference (REF)
The 2V reference is accurate to ±1% over temperature
and load, making REF useful as a precision system ref-
erence. Bypass REF to GND with a 0.22µF or greater
ceramic capacitor. The reference sources up to 100µA
and sinks 10µA to support external loads. If highly
accurate specifications (±0.5%) are required for the
main SMPS output voltages, the reference should not
be loaded. Loading the reference reduces the LDO5,
LDO3, OUT5, and OUT3 output voltages slightly
because of the reference load-regulation error.
System Enable/Shutdown (SHDN)
Drive SHDN below the precise SHDN input falling-edge
trip level to place the MAX1533/MAX1537 in their low-
power shutdown state. The MAX1533/MAX1537 con-
sume only 5µA of quiescent current while in shutdown
mode. When shutdown mode activates, the reference
turns off, making the threshold to exit shutdown less
accurate. To guarantee startup, drive SHDN above
2.2V (SHDN input rising-edge trip level). For automatic
shutdown and startup, connect SHDN to V_IN. The accu-
rate 1V falling-edge threshold on SHDN can be used to
detect a specific input-voltage level and shut the
device down. Once in shutdown, the 1.6V rising-edge
threshold activates, providing sufficient hysteresis for
most applications.
SMPS Detailed
Description
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when V_CC rises above
approximately 1V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled
low if OVP is disabled (OVP = V_CC), or driven high if
OVP is enabled (OVP = GND) until the SMPS con-
trollers are activated.
The V_CC input undervoltage-lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (LDO5) is below
the 4V input UVLO threshold. Once the 5V bias supply
(LDO5) rises above this input UVLO threshold and the
controllers are enabled, the SMPS controllers start
switching and the output voltages begin to ramp up
using soft-start.
The internal digital soft-start gradually increases the
internal current-limit level during startup to reduce the
input surge currents. The MAX1533/MAX1537 divide the
soft-start period into five phases. During the first phase,
each controller limits its current limit to only 20% of its
full current limit. If the output does not reach regulation
within 128 clock cycles (1 / f_OSC), soft-start enters the
second phase and the current limit is increased by
another 20%. This process repeats until the maximum
current limit is reached after 512 clock cycles (1 / f_OSC)
or when the output reaches the nominal regulation volt-
age, whichever occurs first (see the startup waveforms
in the Typical Operating Characteristics).
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