DS3170_11 Datasheet, PDF (25/230 Pages) Maxim Integrated Products – DS3/E3 Single-Chip Transceiver Single-Chip Transceiver for DS3 and E3

DS3170 DS3/E3 Single-Chip Transceiver
8 PIN DESCRIPTIONS
Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for
isolation of interconnect failures.
8.1 Short Pin Descriptions
Table 8-1. DS3170 Short Pin Descriptions
Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog input), IO (Bidirectional in/out)
NAME
PIN
LINE I/O
TLCLK
B7
TPOS/TDAT
E9
TNEG
D9
TXP
E1, E2
TXN
F1, F2
RLCLK
A8
RXP
A4
RXN
A3
RPOS/RDAT
F10
RNEG/RLCV
F9
DS3/E3 OVERHEAD INTERFACE
TOH
C7
TOHEN
E10
TOHCLK
D7
TOHSOF
G9
ROH
B6
ROHCLK
C9
ROHSOF
F8
DS3/E3 SERIAL DATA
TCLKI
C10
TSOFI
A9
TSER
B10
TCLKO/TGCLK
B9
TSOFO/TDEN
C8
RSER
C6
RCLKO/RGCLK
A6
RSOFO/RDEN
B8
MICROPROCESSOR INTERFACE
D[15]
G8
D[14]
H10
D[13]
H9
D[12]
H8
D[11]
J10
D[10]
J9
D[9]
G6
TYPE
FUNCTION
O
Transmit Line Clock Output
O
Transmit Positive AMI/Data
O
Transmit Negative AMI
Oa Transmit Positive analog
Oa Transmit Negative analog
I
Receive Clock Input
Ia
Receive Positive Analog
Ia
Receive Negative Analog
Ia
Positive AMI/Data
Ia
Negative AMI/Line Code Violation
I
Transmit Overhead
I
Transmit Overhead Enable
O
Transmit Overhead Clock
O
Transmit Overhead Start Of Frame
O
Receive Overhead
O
Receive Overhead Clock
O
Receive Overhead Start Of Frame
I
Transmit Line Clock Input
I
Transmit Start Of Frame Input
I
Transmit Serial Data
O
Transmit Clock Output/Gapped Clock
O
Transmit Framer Start Of Frame/Data Enable
O
Receive Serial Data
O
Receive/Clock Output/Gapped Clock
O
Receive Framer Start Of Frame/Data Enable
IO Data [15]
IO Data [14]
IO Data [13]
IO Data [12]
IO Data [11]
IO Data [10]
IO Data [9]
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