DS3170_11 Datasheet, PDF (147/230 Pages) Maxim Integrated Products – DS3/E3 Single-Chip Transceiver Single-Chip Transceiver for DS3 and E3

DS3170 DS3/E3 Single-Chip Transceiver
TEIR[2:0]
000
001
010
011
100
101
110
111
Error Rate
Disabled
1*10^-1
1*10^-2
1*10^-3
1*10^-4
1*10^-5
1*10^-6
1*10^-7
Bit 2: Bit Error Insertion Enable (BEI) – When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) – This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be
inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause a bit error to be inserted.
Register Name:
Register Description:
Register Address:
BERT.SR
BERT Status Register
06Ch
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
PMS
--
BEC
OOS
Bit 3: Performance Monitoring Update Status (PMS) – This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS
will be forced low when the LPMU bit (PMUM = 0) or the global or port PMU bit (PMUM=1) goes low.
Bit 1: Bit Error Count (BEC) – When 0, the bit error count is zero. When 1, the bit error count is one or more.
This bit is cleared when the user updates the BERT counters via the PMU bit (BERT.CR).
Bit 0: Out Of Synchronization (OOS) – When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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