DS3181 Datasheet, PDF (247/389 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

DS3181/DS3182/DS3183/DS3184
12.5 BERT
12.5.1 BERT Register Map
The BERT uses 12 registers.
Note: The BERT registers will be cleared when GL.CR1.RSTDP or PORT.CR1.RSTDP or PORT.CR1.PD is set.
Table 12-24. BERT Register Map
ADDRESS
(0,2,4,6)60h
(0,2,4,6)62h
(0,2,4,6)64h
(0,2,4,6)66h
(0,2,4,6)68h
(0,2,4,6)6Ah
(0,2,4,6)6Ch
(0,2,4,6)6Eh
(0,2,4,6)70h
(0,2,4,6)72h
(0,2,4,6)74h
(0,2,4,6)76h
(0,2,4,6)78h
(0,2,4,6)7Ah
(0,2,4,6)7Ch
(0,2,4,6)7Eh
REGISTER
REGISTER DESCRIPTION
BERT.CR BERT Control Register
BERT.PCR BERT Pattern Configuration Register
BERT.SPR1 BERT Seed/Pattern Register #1
BERT.SPR2 BERT Seed/Pattern Register #2
BERT.TEICR BERT Transmit Error Insertion Control Register
--
Unused
BERT.SR BERT Status Register
BERT.SRL BERT Status Register Latched
BERT.SRIE BERT Status Register Interrupt Enable
--
Unused
BERT.RBECR1 BERT Receive Bit Error Count Register #1
BERT.RBECR2 BERT Receive Bit Error Count Register #2
BERT.RBCR1 BERT Receive Bit Count Register #1
BERT.RBCR2 BERT Receive Bit Count Register #2
--
Unused
--
Unused
12.5.2 BERT Register Bit Descriptions
Register Name:
Register Description:
Register Address:
BERT.CR
BERT Control Register
(0,2,4,6)60h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Default
0
0
0
0
0
0
0
0
Bit #
Name
Default
7
PMUM
0
6
LPMU
0
5
RNPL
0
4
RPIC
0
3
MPR
0
2
APRD
0
1
TNPL
0
0
TPIC
0
Bit 7: Performance Monitoring Update Mode (PMUM) – When 0, a performance monitoring update is initiated by
the LPMU register bit. When 1, a performance monitoring update is initiated by the global or port PMU register bit.
Note: If the LPMU bit or the global or port PMU bit is one, changing the state of this bit may cause a performance
monitoring update to occur.
Bit 6: Local Performance Monitoring Update (LPMU) – This bit causes a performance monitoring update to be
initiated if local performance monitoring update is enabled (PMUM = 0). A 0 to 1 transition causes the performance
monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second performance
monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit
goes high; an update might not be performed. This bit has no affect when PMUM=1.
Bit 5: Receive New Pattern Load (RNPL) – A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0]) to be loaded in to the receive pattern generator. This bit
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