DS3181 Datasheet, PDF (245/389 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

DS3181/DS3182/DS3183/DS3184
Bit 1: PLCP Status Register Interrupt Status (PPSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active PLCP block are set. The interrupt pin will be driven when this bit is set
and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Bit 0: Framer Status Register Interrupt Status (FMSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active DS3 or E3 framer block are set. The interrupt pin will be driven when this
bit is set and the corresponding GL.ISRIE.PISRIE[4:1] is set.
Register Name:
Register Description:
Register Address:
Bit #
15
Name
--
Bit #
7
Name
--
PORT.SR
Port Status Register
(0,2,4,6)52h
14
13
12
--
--
--
6
5
4
--
--
--
11
10
9
8
--
--
--
--
3
2
1
0
--
TDM
RLOL
PMS
Bit 2: Transmit Driver Monitor Status (TDM) This bits indicates the status of the transmit monitor circuit in the
transmit LIU.
0 = Transmit output not over loaded
1 = Transmit signal is overloaded
Bit 1: Receive Loss Of Lock Status (RLOL) This bits indicates the status of the receive LIU clock recovery PLL
circuit.
0 = Locked to the incoming signal
1 = Not locked to the incoming signal
Bit 0: Performance Monitoring Update Status (PMS) This bits indicates the status of all active performance
monitoring register and counter update signals in this port. It is an “AND” of all update status bits and is not set until
all performance registers are updated and the counters reset. In software update modes, the update request bit
PORT.CR1.PMU should be held high until this status bit goes high.
0 = The associated update request signal is low
1 = The requested performance register updates are all completed
Register Name:
Register Description:
Register Address:
PORT.SRL
Port Status Register Latched
(0,2,4,6)54h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Bit #
7
6
5
4
3
2
1
0
Name
RLCLKA TCLKIA
--
--
--
TDML
RLOLL
PMSL
Bit 7: Receive Line Clock Activity Status Latched (RLCLKA) This bit will be set when the signal on the RLCLKn
pin or the recovered clock from the LIU for this port is active.
Bit 6: Transmit Input Clock Activity Status Latched (TCLKIA) This bit will be set when the signal on the TCLKIn
pin for this port is active.
Bit 2: Transmit Driver Monitor Status Latched (TDML) This bit will be set when the PORT.SR.TDM status bit
changes from low to high. This bit will also set the PORT.ISR.PSR status bit if the PORT.SRIE.TDMIE bit is
enabled. The interrupt pin will be driven when this bit is set, the PORT.SRIE.TDMIE bit is set, and the
corresponding GL.ISRIE.PISRIE[4:1] bit is also set.
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