DS3181 Datasheet, PDF (240/389 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

Register Name:
Register Description:
Register Address:
Bit #
15
Name
--
Default
0
Bit #
Name
Default
7
P8KRS1
0
PORT.CR3
Port Control Register 3
(0,2,4,6)44h
14
13
12
--
RCLKS RSOFOS
0
0
0
6
P8KRS0
0
5
P8KREF
0
4
LOOPT
0
11
RPFPE
0
3
CLADC
0
DS3181/DS3182/DS3183/DS3184
10
TCLKS
0
2
RFTS
0
9
TSOFOS
0
1
TFTS
0
8
TPFPE
0
0
TLTS
0
Bit 13: Receive Clock Output Select (RCLKS). This bit is used to select the function of the RPOHCLKn /
RGCLKn / RCLKOn pins. See Table 10-31.
0 = Selects the RGCLKn signal, RPOHCLKn signal, or the drive low pin function.
1 = Selects RCLKOn signal.
Bit 12: Receive Start Of Frame Output Select (RSOFOS). This bit is to select the function of the RSOFOn /
RDENn pins. See Table 10-30.
0 = Selects RDENn signal.
1 = Selects RSOFOn signal.
Bit 11: Receive PLCP/Fractional Port Enable (RPFPE). This bit is used to enable the receive PLCP/Fractional
port pins. See tables in section 10.5.9.2.
0 = Disable receive PLCP/Fractional port pins
1 = Enable receive PLCP/Fractional port pins
Bit 10: Transmit Clock Output Select (TCLKS). This bit is used to select the function of the TPOHCLKn /
TGCLKn / TCLKOn pins. See Table 10-24.
0 = Selects TGCLKn or TPOHCLKn signal.
1 = Selects TCLKOn signal.
Bit 9: Transmit Start Of Frame Output Select (TSOFOS). This bit is used to select the function of the TSOFOn /
TDENn pins. See Table 10-23.
0 = Selects TDENn signal.
1 = Selects TSOFOn signal.
Bit 8: Transmit PLCP/Fractional Port Enable (TPFPE). This bit is used to enable the transmit PLCP/fractional
port pins. See tables in section 10.5.9.1.
0 = Disable transmit PLCP/Fractional port pins
1 = Enable transmit PLCP/Fractional port pins
Bits 7 and 6: Port 8 kHz Reference Source Select [1:0] (P8KRS [1:0]). These bits select the source of the 8 kHz
reference from the port sources. The 8K reference for this port can be used as the global 8K reference source. See
Table 10-13 below.
PORT.CR3.P8KRS[1:0]
0X
10
11
SOURCE
Receive PLCP 8kHZ output
Receive internal framer clock (based on RLCLKn
pin or RX LIU recovered clock)
Transmit internal framer clock (based on TCLKIn
pin or CLAD clock)
Bit 5: Port 8 kHz Reference Source (P8KREF). This bit selects the source of the 8 kHz reference for PLCP trailer
operation and one second timer.
0 = 8 kHz reference from global source
1 = 8 kHz reference from this ports selected source
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