MAX14824 Datasheet, PDF (23/28 Pages) Maxim Integrated Products – IO-Link Master Transceiver

MAX14824
IO-Link Master Transceiver
Table 6. Auto Wake-Up Polarity Generation
WuEnBit
0
0
1
1
WUEN
Low
High
Low
High
Normal operation
Wake-up generation mode
Wake-up generation mode
Wake-up generation mode
MODE
SPI Interface
The device communicates through an SPI-compatible
4-wire serial interface. The interface has three inputs—
clock (SCLK), chip select (CS), and data in (SDI)—and
one output, data out (SDO). The maximum SPI clock rate
for the device is 12MHz. The SPI interface complies with
clock polarity CPOL = 0 and clock phase CPHA = 0 (see
Figure 8 and Figure 9).
The SPI interface is not available when V₅ or V_L is not
present.
CS
SCLK
SDI
W
0
A3
A2
A1
A0
R1
R0
D7
D6
D5
D4
D3
D2
D1
D0
A_ = DEVICE ADDRESS
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE WHEN LOGIC IS LATCHED
Figure 8. SPI Write Cycle
CS
SCLK
SDI X
R
0
A3
A2
A1
A0
R1
R0
X
SDO
A_ = DEVICE ADDRESS
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE WHEN LOGIC IS LATCHED
= CLOCK EDGE AT WHICH LOGIC IS WRITTEN
Figure 9. SPI Read Cycle
D7 D6 D5
D4
D3 D2 D1
D0
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