MAX14824 Datasheet, PDF (16/28 Pages) Maxim Integrated Products – IO-Link Master Transceiver

MAX14824
IO-Link Master Transceiver
The HiSlew bit increases the slew rate of the C/Q driver
output. Set HiSlew to 1 for data rates of 230kbps or
higher. Set HiSlew to 0 to reduce the C/Q driver slew rate
and reduce EMI emission and reflections.
The C/Q receiver is always on. Disable the RX output
through the RxDis bit in the CQConfig register. Set the
RxDis bit to 1 to set the RX output high. Set the RxDis bit
to 0 for normal receive operation.
The C/Q receiver has an analog lowpass filter to reduce
high-frequency noise present on the line. Set the RxFilter
bit in the CQConfig register to 0 to set the filter corner
frequency to 500kHz (typ). Set the RxFilter bit to 1 to set
the corner frequency of the filter to 1MHz (typ). Noise
filters are present on both the C/Q and DI receivers and
are controlled simultaneously by the RxFilter bit.
C/Q Fault Detection
The device registers a C/QFault condition under either of
two conditions:
1) When it detects a short circuit for longer than 160µs
(typ). A short condition exists when the C/Q driver’s
load current exceeds the 670mA (typ) current limit.
2) When it detects a voltage level error at the C/Q out-
put. A voltage level error occurs when the C/Q driver
is configured for open-drain operation (NPN or PNP),
the driver is turned off, and the C/Q voltage is not
pulled to exceed the C/Q receiver’s threshold levels
(< 8V or > 13V) by the external supply.
When a C/QFault error occurs, the C/QFault and C/QFaultInt
bits are set, IRQ asserts, and the driver is turned off 240µs
(typ) after the start of the fault condition.
When a short-circuit event occurs on C/Q, the driver
enters autoretry mode. In autoretry mode the device peri-
odically checks if the short is still present and attempts
to correct the driver output. Autoretry attempts last for
350µs (typ) and occur every 26ms (typ).
DI Auxillary Digital Input
DI is a digital input that is Type 1 and Type 3 compliant
when the internal 3.5mA DI current load is enabled. If the
IO-link master system does not require auxilliary digital
inputs, DI can be connected to C/Q as shown in the
Typical Operating Circuits. This reduces the power dissi-
pation when C/Q is operated as a digital input, by enabling
the DI current load instead of the C/Q current load. Di is
tolerant to reverse polarity voltages down to -40V when not
connected to C/Q.
5V and 3.3V Internal Regulators
The device includes two internal current-limited regulators
to generate 5V (V₅) and 3.3V (LDO33). V₅ is specified
at 10mA. LDO33 is specified at 10mA. The input of V₅,
LDOIN, can be connected to V_CC or to another voltage in
the 7V to 36V range.
V₅ consitutes the supply for the logic block in the device.
The device can be powered by an external 5V power
supply. Disable the 5V LDO by connecting LDOIN to V₅.
Apply an external voltage from 4.75V to 5.25V to V₅ when
the LDO is disabled.
Use the LDO33Dis bit in the Mode register to enable/
disable LDO33. See the Mode Register [R1, R0] = [1,1]
section for more information. V₅ and LDO33 are not pro-
tected against short circuits.
Power-Up
The C/Q driver output and the UV output are high imped-
ance when V_CC, V₅, V_L, and/or LDO33 voltages are
below their respective undervoltage thresholds during
power-up. UV goes low and the C/Q driver is enabled
when all these voltages exceed their respective under-
voltage lockout thresholds.
The C/Q driver is automatically disabled if V_CC, V₅, or V_L
falls below its threshold.
Undervoltage Detection
The device monitors V_CC, V₅, V_L, and, optionally, LDO33
for undervoltage conditions. UV is high impedance when
any monitored voltage falls below its UVLO threshold.
V_CC, V_5, and VL undervoltage detection cannot be dis-
abled. When V_CC falls below the V_CCUVLO threshold, the
UV24 and UV24Int bits are set, UV asserts high, and IRQ
asserts low.
The SPI register contents are unchanged while V₅ is
present, regardless of the state of V_CC or LDO33. The SPI
interface is not accessible and IRQ is not available when
UV is asserted due to a V₅ or V_L undervoltage event.
When the internal 3.3V LDO regulator voltage (V_LDO33)
falls below the LDO33 undervoltage lockout threshold,
the UV33Int bit in the Status register is set and IRQ
asserts. UV asserts if the UV33En bit in the Mode register
is set to 1.
The UV output deasserts once the undervoltage condi-
tion is removed; however, the associated interrupts bits
in the Status register and the IRQ output are not cleared
until the Status register has been read.
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