MAX1471_05 Datasheet, PDF (23/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 8. Control Register (Address: 0x2)
BIT ID
X
AGCLOCK
X
FSKTRK_EN
BIT NAME
None
AGC lock
None
FSK peak
detector track
enable
BIT LOCATION
(0 = LSB)
7
6
5, 4
3
POWER-UP
STATE
Don’t care
0
0
ASK peak
ASKTRK_EN detector track
2
0
enable
POL_CAL_EN
Polling timer
calibration enable
1
0
FSK_CAL_EN
FSK calibration
enable
0
0
FUNCTION
Don’t care.
Locks the LNA gain in its present state.
Don’t care.
Enables the tracking mode of the FSK peak detectors
when FSKTRK_EN = 1. (See the Peak Detectors
section.)
Enables the tracking mode of the ASK peak detectors
when ASKTRK_EN = 1.
(See the Peak Detectors section.)
POL_CAL_EN = 1 starts the polling timer calibration.
Calibration of the polling timer is needed when using
the MAX1471 in discontinous receive mode.
POL_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
FSK_CAL_EN starts the FSK receiver calibration.
FSK_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
Table 9. Status Register (Read Only) (Address: 0x9)
BIT ID
BIT NAME
BIT LOCATION
(0 = LSB)
FUNCTION
LOCKDET
Lock detect
AGCST
AGC state
CLKALIVE
X
POL_CAL_DONE
FSK_CAL_DONE
Clock/crystal
alive
None
Polling timer
calibration done
FSK calibration
done
7
6
5
4, 3, 2
1
0
0 = Internal PLL is not locked so the MAX1471 will not receive data.
1 = Internal PLL is locked.
0 = LNA in low-gain state.
1 = LNA in high-gain state.
0 = No valid clock signal seen at the crystal inputs.
1 = Valid clock at crystal inputs.
Don’t care.
0 = Polling timer calibraton in progress or not completed.
1 = Polling timer calibration is complete.
0 = FSK calibration in progress or not completed.
1 = FSK calibration is compete.
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