MAX1471_05 Datasheet, PDF (14/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 2. Coefficients to Calculate CF1
and CF2
FILTER TYPE
a
b
Butterworth
(Q = 0.707)
1.414
1.000
Bessel
(Q = 0.577)
1.3617
0.618
MAX1471
RSSI OR
FSK DEMOD
100kΩ
100kΩ
DSA+
DSF+
OPA+
DFA
OPF+
DFF
C_F2
C_F1
Figure 3. Sallen-Key Lowpass Data Filter
MAX1471
DATA
SLICER
ADATA
FDATA
DSA-
DSF-
C
R
DSA+
DSF+
Figure 4. Generating Data-Slicer Threshold Using a Lowpass
Filter
With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.
Figure 5 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Peak Detectors
The maximum peak detectors (PDMAXA for ASK,
PDMAXF for FSK) and minimum peak detectors (PDMI-
NA for ASK, PDMINF for FSK), in conjunction with resis-
tors and capacitors shown in Figure 5, create DC
output voltages proportional to the high and low peak
values of the filtered ASK or FSK demodulated signals.
The resistors provide a path for the capacitors to dis-
charge, allowing the peak detectors to dynamically fol-
low peak changes of the data-filter output voltages.
The maximum and minimum peak detectors can be
used together to form a data-slicer threshold voltage at
a midvalue between the maximum and minimum volt-
age levels of the data stream (see the Data Slicers sec-
tion and Figure 5). The RC time constant of the peak-
detector combining network should be set to at least 5
times the data period.
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX1471 has a fea-
ture called peak-detector track enable (TRK_EN),
where the peak-detector outputs can be reset (see
Figure 6). If TRK_EN is set (logic 1), both the maximum
and minimum peak detectors follow the input signal.
When TRK_EN is cleared (logic 0), the peak detectors
revert to their normal operating mode. The TRK_EN
function is automatically enabled for a short time and
then disabled whenever the IC recovers from the sleep
portion of DRX mode, or when an AGC gain switch
occurs. Since the peak detectors exhibit a fast
attack/slow decay response, this feature allows for an
extremely fast startup or AGC recovery. See Figure 7
for an illustration of a fast-recovery sequence. In addi-
tion to the automatic control of this function, the
TRK_EN bits can be controlled through the serial inter-
face (see the Serial Control Interface section).
Power-Supply Connections
The MAX1471 can be powered from a 2.4V to 3.6V sup-
ply or a 4.5V to 5.5V supply. The device has an on-chip
linear regulator that reduces the 5V supply to 3V need-
ed to operate the chip.
To operate the MAX1471 from a 3V supply, connect
DV_DD, AV_DD, and HV_IN to the 3V supply. When using a
5V supply, connect the supply to HV_IN only and con-
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