MAX1471_05 Datasheet, PDF (10/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Detailed Description
The MAX1471 CMOS superheterodyne receiver and a
few external components provide a complete ASK/FSK
receive chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 33kbps using Manchester Code
(66kbps nonreturn to zero) can be achieved.
The MAX1471 is designed to receive binary FSK or
ASK data on a 300MHz to 450MHz carrier. ASK modu-
lation uses a difference in amplitude of the carrier to
represent logic 0 and logic 1 data. FSK uses the differ-
ence in frequency of the carrier to represent a logic 0
and logic 1.
Low-Noise Amplifier (LNA)
The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 28dB of volt-
age gain that is dependent on both the antenna-match-
ing network at the LNA input, and the LC tank network
between the LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by con-
necting an inductor from LNASRC to AGND. This induc-
tor sets the real part of the input impedance at LNAIN,
allowing for a flexible match to low input impedances
such as a PC board trace antenna. A nominal value for
this inductor with a 50Ω input impedance is 15nH at
315MHz and 10nH at 434MHz, but the inductance is
affected by PC board trace length. See the Typical
Operating Characteristics to see the relationship
between the inductance and input impedance. The
inductor can be shorted to ground to increase sensitivi-
ty by approximately 1dB, but the input match is not
optimized for 50Ω.
The LC tank filter connected to LNAOUT comprises L2
and C9 (see the Typical Application Circuit). Select L2
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
f=
1
2π ^LTOTAL ^{× C}TOTAL
where L_TOTAL = L2 + L_PARASITICS and C_TOTAL = C9 +
C_PARASITICS.
L_PARASITICS and C_PARASITICS include inductance and
capacitance of the PC board traces, package pins,
mixer input impedance, LNA output impedance, etc.
These parasitics at high frequencies cannot be
ignored, and can have a dramatic effect on the tank fil-
ter center frequency. Lab experimentation should be
done to optimize the center frequency of the tank.
Automatic Gain Control (AGC)
When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre-
sponds to an RF input level of approximately -64dBm,
the AGC switches on the LNA gain reduction attenuator.
The attenuator reduces the LNA gain by 35dB, thereby
reducing the RSSI output by about 0.55V. The LNA
resumes high-gain mode when the RSSI output level
drops back below 0.68V (approximately -67dBm at the
RF input) for a programmable interval called the AGC
dwell time. The AGC has a hysteresis of approximately
3dB. With the AGC function, the RSSI dynamic range is
increased, allowing the MAX1471 to reliably produce an
ASK output for RF input levels up to 0dBm with a modu-
lation depth of 18dB. AGC is not necessary and can be
disabled when utilizing only the FSK data path.
The MAX1471 features an AGC lock controlled by the
AGC lock bit (see Table 8). When the bit is set, the LNA
is locked in its present gain state.
Mixer
A unique feature of the MAX1471 is the integrated
image rejection of the mixer. This device was designed
to eliminate the need for a costly front-end SAW filter for
many applications. The advantage of not using a SAW
filter is increased sensitivity, simplified antenna match-
ing, less board space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., f_LO = f_RF - f_IF). The image-rejection circuit
then combines these signals to achieve approximately
45dB of image rejection. Low-side injection is required
as high-side injection is not possible due to the on-chip
image rejection. The IF output is driven by a source fol-
lower, biased to create a driving impedance of 330Ω to
interface with an off-chip 330Ω ceramic IF filter. The
voltage conversion gain driving a 330Ω load is approxi-
mately 19.5dB. Note that the MIXIN+ and MIXIN- inputs
are functionally identical.
Phase-Locked Loop (PLL)
The PLL block contains a phase detector, charge
pump/integrated loop filter, voltage-controlled oscillator
(VCO), asynchronous 32x clock divider, and crystal
oscillator. This PLL does not require any external com-
ponents. The relationship between the RF, IF, and refer-
ence frequencies is given by:
f_REF = (f_RF - f_IF)/32
To allow the smallest possible IF bandwidth (for best sen-
sitivity), the tolerance of the reference must be minimized.
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