MAX16930 Datasheet, PDF (21/29 Pages) Maxim Integrated Products – 2MHz, 36V, Dual Buck with Preboost and 20μA Quiescent Current

MAX16930/MAX16931
2MHz, 36V, Dual Buck with Preboost and
20µA Quiescent Current
CS_
OUT_
g_mc = 1/(AVCS x RDC)
CURRENT MODE
POWER
MODULATION
R1
RESR
FB_
g_mea = 1200µS
COUT
R2
ERROR
AMP
VREF
30MI
COMP_
RC
CF
CC
Figure 2. Compensation Network
The basic regulator loop is modeled as a power modula-
tor, output feedback divider, and an error amplifier as
shown in Figure 2. The power modulator has a DC gain
set by g_mc x R_LOAD, with a pole and zero pair set by
R_LOAD, the output capacitor (C_OUT), and its ESR. The
loop response is set by the following equations:
GAIN_MOD(= _dc) g_mc × R_LOAD
where R_LOAD = V_OUT/I_LOUT(MAX) in I and g_mc =1/(A_{V_}
CS ^{x R}DC^{) in S. A}V_CS ^{is the voltage gain of the current-}
sense amplifier and is typically 11V/V. R_DC is the DC
resistance of the inductor or the current-sense resistor in
I.
In a current-mode step-down converter, the output
capacitor and the load resistance introduce a pole at the
following frequency:
f_pMOD
=
2π
×
1
C_OUT × R_LOAD
The unity gain frequency of the power stage is set by
C_OUT and g_mc:
f_UGAINpMOD
=
g_mc
2π × C_OUT
The output capacitor and its ESR also introduce a zero at:
f_zMOD
=
2π
×
1
ESR ×
C_OUT
When C_OUT is composed of “n” identical capacitors in
parallel, the resulting C_OUT = nxC_OUT(EACH), and ESR =
ESR_(EACH)/n. Note that the capacitor zero for a parallel
combination of alike capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GAIN_FB = V_FB/
V_OUT, where V_FB is 1V (typ).
The transconductance error amplifier has a DC gain of
GAIN_EA(DC) = g_m,EA x R_OUT,EA, where g_m,EA is the error
amplifier transconductance, which is 1200µS (typ), and
R_OUT,EA is the output resistance of the error amplifier, which
is 30MI (typ) (see the Electrical Characteristics table.)
A dominant pole (f_dpEA) is set by the compensa-
tion capacitor (C_C) and the amplifier output resistance
(R_OUT,EA). A zero (f_ZEA) is set by the compensation
resistor (R_C) and the compensation capacitor (C_C).
There is an optional pole (f_PEA) set by C_F and R_C to
cancel the output capacitor ESR zero if it occurs near
the crossover frequency (f_C, where the loop gain equals
1 (0dB)). Thus:
f_dpEA
=
2π × C_C
1
× (R_OUT,EA
+ R_C)
f_zEA
=
2π ×
1
C_C
×R_C
f_pEA
=
1
2π × C_F
×R_C
The loop-gain crossover frequency (f_C) should be set
below 1/5th of the switching frequency and much higher
than the power-modulator pole (f_pMOD). Select a value
for f_C in the range:
f_pMOD
<<
f_C
≤
f_SW
5
Maxim Integrated
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