MAX16930 Datasheet, PDF (14/29 Pages) Maxim Integrated Products – 2MHz, 36V, Dual Buck with Preboost and 20μA Quiescent Current

MAX16930/MAX16931
2MHz, 36V, Dual Buck with Preboost and
20µA Quiescent Current
Switching Frequency/External
Synchronization
The MAX16930 provides an internal oscillator adjust-
able from 1MHz to 2.2MHz. The MAX16931 provides
an internal oscillator adjustable from 200kHz to 1MHz.
High-frequency operation optimizes the application for
the smallest component size, trading off efficiency to
higher switching losses. Low-frequency operation offers
the best overall efficiency at the expense of component
size and board space. To set the switching frequency,
connect a resistor R_FOSC from FOSC to AGND. See
TOCs 8 and 9 in the Typical Operating Characteristics
section to determine the relationship between switching
frequency and R_FOSC.
Buck 1 and the boost converter are synchronized with
the internal clock-signal rising edge, while buck 2 is
synchronized with the clock-signal falling edge. The
preboost enables the low-side switch (DL3) with the ris-
ing edge of the cycle while buck 1 turns on its high-side
n-channel MOSFET (DH1).
The devices can be synchronized to an external clock
by connecting the external clock signal to FSYNC. A
rising edge on FSYNC resets the internal clock. Keep
the FSYNC frequency between 110% and 125% of the
internal frequency. The FSYNC signal should have a 50%
duty cycle.
Light-Load Efficiency Skip Mode
(V_FSYNC = 0V)
Drive FSYNC low to enable skip mode. In skip mode, the
devices stop switching until the FB voltage drops below
the reference voltage. Once the FB voltage has dropped
below the reference voltage, the devices begin switching
until the inductor current reaches 30% (skip threshold)
of the maximum current defined by the inductor DCR or
output shunt resistor.
Forced-PWM Mode (V_FSYNC)
Driving FSYNC high prevents the devices from enter-
ing skip mode by disabling the zero-crossing detection
of the inductor current. This forces the low-side gate-
driver waveform to constantly be the complement of
the high-side gate-drive waveform, so the inductor cur-
rent reverses at light loads and discharges the output
capacitor. The benefit of forced PWM mode is to keep the
switching frequency constant under all load conditions.
However, forced-frequency operation diverts a consider-
able amount of the output current to PGND, reducing the
efficiency under light-load conditions.
Forced-PWM mode is useful for improving load-transient
response and eliminating unknown frequency harmonics
that can interfere with AM radio bands.
Spread Spectrum
The MAX16930AGLS/MAX16930AGLU/MAX16931AGLS
feature enhanced EMI performance. They perform Q6%
dithering of the switching frequency to reduce peak
emission noise at the clock frequency and its harmonics,
making it easier to meet stringent emission limits.
When using an external clock source (i.e., driving the
FSYNC input with an external clock), spread spectrum
is disabled.
Buck 2 Switching Frequency
For the MAX16930ATLT and MAX16930ATLU, the switch-
ing frequency of buck 2 is set to 1/2 of f_SW (buck 1 switch-
ing frequency). When using these devices, the external
components of buck 2 should be sized to account for
the reduced switching frequencies (see the Design
Procedure section).
MOSFET Gate Drivers (DH_ and DL_)
The DH_ high-side n-channel MOSFET drivers are pow-
ered from capacitors at BST_ while the low-side drivers
(DL_) are powered by the 5V linear regulator (BIAS). On
each channel, a shoot-through protection circuit monitors
the gate-to-source voltage of the external MOSFETs to
prevent a MOSFET from turning on until the complemen-
tary switch is fully off. There must be a low-resistance,
low-inductance path from the DL_ and DH_ drivers to the
MOSFET gates for the protection circuits to work properly.
Follow the instructions listed to provide the necessary low-
resistance and low-inductance path:
• Use very short, wide traces (50 mils to 100 mils wide
if the MOSFET is 1in from the driver).
It may be necessary to decrease the slew rate for the
gate drivers to reduce switching noise or to compensate
for low-gate charge capacitors. For the low-side drivers,
use gate capacitors in the range of 1nF to 5nF from DL_
to GND. For the high-side drivers, connect a small 5I to
10I resistor between BST_ and the bootstrap capacitor.
Note: Gate drivers must be protected during shutdown,
at the absence of the supply voltage (V_BIAS = 0V) when
the gate is pulled high either capacitively or by the leak-
age path on the PCB. Therefore, external gate pulldown
resistors are needed, especially at DL3 to prevent mak-
ing a direct path from V_BAT to GND.
Maxim Integrated
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