DS1315 Datasheet, PDF (20/21 Pages) Dallas Semiconductor – Phantom Time Chip

PIN CONFIGURATIONS (continued)
DS1315 Phantom Time Chip
X1
X2
WE
BAT1
GND
D
Q
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
16-Pin SO (300 mil)
V_CC1
V_CC0
BAT2
RST
OE
CEI
CEO
ROM/RAM
X1
X2
WE
NC
BAT1
GND
NC
D
Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
20-Pin TSSOP
V_CC1
V_CC0
BAT2
NC
RST
OE
NC
CEI
CEO
ROM/RAM
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
16 PDIP
P16+1
21-0043
—
16 TSSOP
U20+1
21-0066
90-0116
16 SO
W16+2
21-0042
90-0107
20 of 21