DS1315 Datasheet, PDF (18/21 Pages) Dallas Semiconductor – Phantom Time Chip

DS1315 Phantom Time Chip
NOTES:
1) All voltages are referenced to ground.
2) Measured with load shown in Figure 15.
3) Input pulse rise and fall times equal 10ns.
4) t_WR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM
mode.
5) t_DH and t_DS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in
ROM mode.
6) Measured without RAM connected.
7) I_CCO1 is the maximum average load current the DS1315 can supply to external memory.
8) Applies to CEO with the ROM/ RAM pin grounded. When the ROM/ RAM pin is connected to V_CCO,
CEO will go to a low level as V_CCI falls below V_BAT.
9) I_CCO2 is the maximum average load current that the DS1315 can supply to memory in the battery
backup mode.
10) Applies to all input pins except RST . RST is pulled internally to V_CCI.
11) See Figures 11 and 12.
12) See Figures 13 and 14.
13) V_SW is determined by the larger of V_BAT1 and V_BAT2.
14) V_SW is determined by the smaller of V_BAT1, V_BAT2, and V_PF.
Figure 13. 3.3V Power-Up Condition
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