MAX11626_1110 Datasheet, PDF (19/22 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with FIFO and Internal Reference

12-Bit, 300ksps ADCs
with FIFO and Internal Reference
DIN
CS
SCLK
(CONVERSION BYTE)
(ACQUISITION1)
(CONVERSION1)
(ACQUISITION2)
DOUT
MSB1
LSB1
MSB2
EOC
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Figure 7. Clock Mode 11 Timing
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eight and ninth cycles, the pulse
width must be less than 100µs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
If reference mode 00 is requested, wait 65µs with CS
high after writing the conversion byte to extend the
acquisition and allow the internal reference to power up.
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Transfer Function
Figure 8 shows the unipolar transfer function. Code tran-
sitions occur halfway between successive-integer LSB
values. Output coding is binary, with 1 LSB = V_REF/2.5V
(MAX11627/MAX11629/MAX11633) and 1 LSB = V_REF/
4.096V (MAX11626/MAX11628/MAX11632).
OUTPUT CODE
11 . . . 111
11 . . . 110
11 . . . 101
FULL-SCALE
TRANSITION
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
01
(COM)
23
INPUT VOLTAGE (LSB)
FS = V_REF + V_COM
ZS = V_COM
1 LSB = ^VREF
4096
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V_REF
Layout, Grounding, and Bypassing
For best performance, use PCBs. Do not use wire wrap
boards. Board layout should ensure that digital and ana-
log signal lines are separated from each other. Do not
run analog and digital (especially clock) signals parallel
to one another or run digital lines underneath the
MAX11626–MAX11629/MAX11632/MAX11633 package.
High-frequency noise in the V_DD power supply can
affect performance. Bypass the V_DD supply with a 0.1µF
capacitor to GND, close to the V_DD pin. Minimize capaci-
tor lead lengths for best supply-noise rejection. If the
power supply is very noisy, connect a 10Ω resistor in
series with the supply to improve power-supply filtering.
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