MAX11626_1110 Datasheet, PDF (10/22 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with FIFO and Internal Reference

12-Bit, 300ksps ADCs
with FIFO and Internal Reference
Pin Description
MAX11626
MAX11627
(4 CHANNELS)
5, 6, 7
—
—
1–4
—
—
8
9
10
11
12
13
14
15
16
MAX11628
MAX11629
(8 CHANNELS)
—
—
1–7
—
—
8
—
9
10
11
12
13
14
15
16
MAX11632
MAX11633
(16 CHANNELS)
—
1–15
—
—
16
—
—
17
18
19
20
21
22
23
24
NAME
FUNCTION
N.C.
AIN0–AIN14
AIN0–AIN6
AIN0–AIN3
CNVST/AIN15
No Connection. Not internally connected.
Analog Inputs
Analog Inputs
Analog Inputs
Active-Low Conversion Start Input/Analog Input 15.
See Table 3 for details on programming the setup
register.
CNVST/AIN7
Active-Low Conversion Start Input/Analog Input 7.
See Table 3 for details on programming the setup
register.
CNVST
REF
GND
V_DD
CS
Active-Low Conversion Start Input. See Table 3 for
details on programming the setup register.
Reference Input. Bypass to GND with a 0.1µF
capacitor.
Ground
Power Input. Bypass to GND with a 0.1µF
capacitor.
Active-Low Chip-Select Input. When CS is low, the
serial interface is enabled. When CS is high, DOUT
is high impedance.
SCLK
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See
Table 3 for details on programming the clock mode.
DIN
DOUT
EOC
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
Serial Data Output. Data is clocked out on the falling
edge of SCLK. High impedance when CS is
connected to V_DD.
End of Conversion Output. Data is valid after EOC
pulls low.
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