MAX11626_1110 Datasheet, PDF (18/22 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with FIFO and Internal Reference

12-Bit, 300ksps ADCs
with FIFO and Internal Reference
CNVST
(ACQUISITION1)
CS
(ACQUISITION2)
SCLK
(CONVERSION1)
(CONVERSION2)
DOUT
MSB1
EOC
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION.
Figure 5. Clock Mode 01 Timing
LSB1
MSB2
DIN
CS
SCLK
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DOUT
MSB1
LSB1
MSB2
EOC
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED.
Figure 6. Clock Mode 10 Timing
Internally Timed Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This
is the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX11626–MAX11629/MAX11632/MAX11633
then power up, scan all requested channels, store the
results in the FIFO, and shut down. After the scan is
complete, EOC is pulled low and the results are avail-
able in the FIFO. EOC stays low until CS is pulled low
again.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
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