MAX106 Datasheet, PDF (19/32 Pages) Maxim Integrated Products – ±5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier

±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
The dynamic performance of the data converter is
essentially unaffected by clock-drive power levels from
-10dBm (100mV clock signal amplitude) to +10dBm
(1V clock signal amplitude). The MAX106 dynamic per-
formance specifications are determined by a single-
ended clock drive of +4dBm (500mV clock signal
amplitude). To avoid saturation of the input amplifier
stage, limit the clock power level to a maximum of
+10dBm.
Differential Clock Inputs (Sine-Wave Drive)
The advantages of differential clock drive (Figure 13b,
Table 5) can be obtained by using an appropriate
balun or transformer to convert single-ended sine-wave
sources into differential drives. The precision on-chip
laser-trimmed 50Ω clock-termination resistors ensure
excellent amplitude matching. See Single-Ended Clock
Inputs (Sine-Wave Drive) for proper input amplitude
requirements.
Single-Ended Clock Inputs (ECL Drive)
Configure the MAX106 for single-ended ECL clock
drive by connecting the clock inputs as shown in Figure
13c (Table 5). A well-bypassed V_BB supply (-1.3V) is
essential to avoid coupling noise into the undriven
clock input, which would degrade the dynamic perfor-
mance.
Differential Clock Inputs (ECL Drive)
The MAX106 may be driven from a standard differential
(Figure 13d, Table 5) ECL clock source by setting the
clock termination voltage at CLKCOM to -2V. Bypass
the clock-termination return (CLKCOM) as close to the
ADC as possible with a 0.01µF capacitor connected to
GNDI.
+0.5V
CLK+
CLK- = 0V
-0.5V
t
NOTE: CLKCOM = 0V
Figure 13a. Single-Ended Clock Input Signals
+0.5V
CLK+
CLK-
-0.5V
t
NOTE: CLKCOM = 0V
Figure 13b. Differential Clock Input Signals
CLK+
-0.8V
CLK- = -1.3V
CLK+
-0.8V
CLK-
-1.8V
NOTE: CLKCOM = -2V
t
-1.8V
t
NOTE: CLKCOM = -2V
Figure 13c. Single-Ended ECL Clock Drive
Figure 13d. Differential ECL Clock Drive
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