MAX106 Datasheet, PDF (15/32 Pages) Maxim Integrated Products – ±5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier

±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Non-Demultiplexed DIV1 Mode
The MAX106 may be operated at up to the full sam-
pling rate (600Msps) in non-demultiplexed DIV1 mode
(Table 2). In this mode, the internal demultiplexer is dis-
abled and sampled data is presented to the primary
port only, with the data repeated at the auxiliary port,
but delayed by one clock cycle (Figure 6). Since the
auxiliary output port contains the same data stream as
the primary output port, the auxiliary port can be shut
down to save power by connecting AUXEN1 and
AUXEN2 to digital ground (GNDD). This powers down
the internal bias cells and causes both outputs (true
and complementary) of the auxiliary port to pull up to a
logic-high level. To save additional power, the external
50Ω termination resistors connected to the PECL termi-
nation power supply (V_CCO - 2V) may be removed from
all auxiliary output ports.
Demultiplexed DIV2 Mode
The MAX106 features an internally selectable DIV2
mode (Table 2) that reduces the output data rate to
one-half of the sample clock rate. The demultiplexed
outputs are presented in dual 8-bit format with two con-
secutive samples appearing in the primary and auxil-
iary output ports on the rising edge of the data-ready
clock (Figure 7). The auxiliary data port contains the
previous sample, and the primary output contains the
most recent data sample. AUXEN1 and AUXEN2 must
be connected to V_CCO to power up the auxiliary port
PECL output drives.
CLK- n
CLK
CLK+
DREADY+
DREADY
DREADY-
AUXILIARY
DATA PORT
ADC SAMPLE NUMBER
n+1
n+2
n+3
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4
n+5
n+6
n+7
n+8
n+9 n+10 n+11 n+12 n+13
n
n+1
n+2
n+3
n+4
PRIMARY
DATA PORT
n+1
n+2
n+3 n+4
n+5
NOTE: THE AUXILIARY PORT DATA IS DELAYED ONE ADDITIONAL CLOCK CYCLE FROM THE PRIMARY PORT DATA.
GROUNDING AUXEN1 AND AUXEN2 WILL POWER DOWN THE AUXILIARY PORT TO SAVE POWER.
Figure 6. Non-Demuxed, DIV1-Mode Timing Diagram
CLK- n
CLK
CLK+
DREADY+
DREADY
DREADY-
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
ADC SAMPLE NUMBER
n+1
n+2
n+3
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4
n+5
n+6
n+7
n+8
n+9
n-1
n
n+10 n+11
n+1
n+2
n+12 n+13
n+3
n+4
NOTE: THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES.
BOTH THE PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
Figure 7. Demuxed DIV2-Mode Timing Diagram
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