MAX15014_07 Datasheet, PDF (18/26 Pages) Maxim Integrated Products – 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators

1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
ESR
=
I_{OUT _}
∆V_ESR
MAX ⁺
∆I_P−P
2
C_IN
=
I_{OUT_MAX} ×
∆V_Q × f_SW
D
where C_IN is the sum of C_DRAIN and additional decou-
pling capacitance at the buck converter input,
∆I_P−P
=
(V_IN − V_OUT) × V_OUT
V_IN × f_SW × L
and
D = ^VOUT
V_IN
I_{OUT_MAX} is the maximum output current, D is the duty
cycle, and f_SW is the switching frequency.
The MAX15014–MAX15017 include UVLO hysteresis
and soft-start to avoid chattering during turn-on.
However, use additional bulk capacitance if the input
source impedance is high. Use enough input capaci-
tance at lower input voltages to avoid possible under-
shoot below the undervoltage lockout threshold during
transient loading.
Output-Capacitor Selection
The allowable output voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the output capacitance (C_OUT) and its equivalent
series resistance (ESR). The output ripple is mainly
composed of ∆V_Q (caused by the capacitor discharge)
and ∆V_ESR (caused by the voltage drop across the ESR
of the output capacitor). The equations for calculating
the peak-to-peak output voltage ripple are:
∆V_Q
=
∆I_P−P
8 × C_OUT × f_SW
∆V_ESR = ESR × ∆I_P−P
Normally, a good approximation of the output voltage rip-
ple is ∆V_RIPPLE = ∆V_ESR + ∆V_Q. If using ceramic capaci-
tors, assume the contribution to the output voltage ripple
from ESR and the capacitor discharge to be equal to 20%
and 80%, respectively. ∆I_P-P is the peak-to-peak inductor
current (see the Input-Capacitor Selection section) and
f_SW is the converter’s switching frequency.
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
greater duty cycle. The response time (t_RESPONSE)
depends on the closed-loop bandwidth of the converter
(see the Compensation Design section). The resistive
drop across the output capacitor’s ESR, the drop
across the capacitor’s ESL (∆V_ESL), and the capacitor
discharge causes a voltage droop during the loadstep.
Use a combination of low-ESR tantalum/aluminum elec-
trolytic and ceramic capacitors for better transient load
and voltage ripple performance. Non-leaded capaci-
tors and capacitors in parallel help reduce the ESL.
Keep the maximum output voltage deviation below the
tolerable limits of the electronics being powered. Use
the following equations to calculate the required ESR,
ESL, and capacitance value during a load step:
ESR = ^∆VESR
I_STEP
C_OUT
=
I_STEP
× t_RESPONSE
∆V_Q
ESL = ^{∆VESL × tSTEP}
I_STEP
t_RESPONSE
≅
1
3ƒ_C
where I_STEP is the load step, t_STEP is the rise time of the
load step, t_RESPONSE is the response time of the con-
troller and f_C is the closed-loop crossover frequency.
Compensation Design
The MAX15014–MAX15017 use a voltage-mode control
scheme that regulates the output voltage by comparing
the error amplifier output (COMP) with an internal ramp
to produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequency,
which has a gain drop of -40dB/decade. The error
amplifier must compensate for this gain drop and
phase shift to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage error amplifier.
The power modulator has a DC gain set by V_IN /
V_RAMP, with a double pole and a single zero set by the
output inductance (L), the output capacitance (C_OUT),
and its ESR. The power modulator incorporates a voltage
feed-forward feature, which automatically adjusts for vari-
ations in the input voltage resulting in a DC gain of 10.
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