MAX12555 Datasheet, PDF (18/28 Pages) Maxim Integrated Products – 14-Bit, 95Msps, 3.3V ADC

14-Bit, 95Msps, 3.3V ADC
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (V_REFP - V_REFN) x 3/4 to (V_REFN - V_REFP) x 3/4.
Signals outside this valid differential range cause DOR
to assert high as shown in Table 2 and Figure 6.
DOR is synchronized with DAV and transitions along
with the output data D13–D0. There is an 8.0 clock-
cycle latency in the DOR function as is with the output
data (Figure 6).
DOR is high impedance when the MAX12555 is in
power-down (PD = high). DOR enters a high-imped-
ance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.
Digital Output Data (D13–D0), Output Format (G/T)
The MAX12555 provides a 14-bit, parallel, tri-state out-
put bus. D13–D0 and DOR update on the falling edge
of DAV and are valid on the rising edge of DAV.
The MAX12555 output data format is either Gray code
or two’s complement, depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is two’s comple-
ment. See Figure 9 for a binary-to-Gray and Gray-to-
binary code-conversion example.
The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:
V_INP − V_INN
= (V_REFP − V_REFN) ×
4
3
× ^{CODE10 − 8192}
16384
for Gray code (G/T = 1).
V_INP − V_INN = (V_REFP − V_REFN) ×
4
3
× ^CODE10
16384
for two’s complement (G/T = 0).
where CODE₁₀ is the decimal equivalent of the digital
output code as shown in Table 2.
Digital outputs D13–D0 are high impedance when the
MAX12555 is in power-down (PD = high). D13–D0 tran-
sition high 10ns after the rising edge of PD and
become active 10ns after PD’s falling edge.
Keep the capacitive load on the MAX12555 digital out-
puts D13–D0 as low as possible (<15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12555 and degrading its dynamic perfor-
mance. The addition of external digital buffers on the
digital outputs isolates the MAX12555 from heavy
capacitive loading. To improve the dynamic perfor-
mance of the MAX12555, add 220Ω resistors in series
with the digital outputs close to the MAX12555. Refer to
the MAX12555 evaluation kit schematic for an example
of the digital outputs driving a digital buffer through
220Ω series resistors.
Power-Down Input (PD)
The MAX12555 has two power modes that are con-
trolled with the power-down digital input (PD). With PD
low, the MAX12555 is in normal operating mode. With
PD high, the MAX12555 is in power-down mode.
The power-down mode allows the MAX12555 to effi-
ciently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12555 parallel output bus is high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
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