MAX12555 Datasheet, PDF (14/28 Pages) Maxim Integrated Products – 14-Bit, 95Msps, 3.3V ADC

14-Bit, 95Msps, 3.3V ADC
CLKP
CLKN
DCE
CLKTYP
INP
INN
REFOUT
REFIN
REFP
COM
REFN
CLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
14-BIT
T/H
PIPELINE
ADC
REFERENCE
SYSTEM
MAX12555
DEC
OUTPUT
DRIVERS
POWER CONTROL
AND
BIAS CIRCUITS
V_DD
GND
OV_DD
D13–D0
DAV
DOR
G/T
PD
Figure 2. Simplified Functional Diagram
Detailed Description
The MAX12555 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output, the total clock-cycle latency is 8.0
clock cycles.
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12555 functional diagram.
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a common-mode input voltage of V_DD / 2 ±0.5V.
The MAX12555 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3) allowing
the analog input signal to be stored as a charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure 4). The analog input
signal source must be capable of providing the dynam-
ic current necessary to charge and discharge the sam-
pling capacitors. To avoid signal degradation, these
BOND WIRE
INDUCTANCE
1.5nH
INP
BOND WIRE
INDUCTANCE
1.5nH
INN
V_DD
MAX12555
C_PAR
*C_SAMPLE
2pF
4.5pF
V_DD
C_PAR
*C_SAMPLE
2pF
4.5pF
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS: R_SAMPLE =
1
f_CLK x C_SAMPLE
Figure 3. Simplified Input T/H Circuit
capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.
The analog input of the MAX12555 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
supply (V_DD / 2). The MAX12555 provides the optimum
common-mode voltage of V_DD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12555. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX12555 or when PD transitions from
high to low. REFOUT has approximately 17kΩ to GND
when the MAX12555 is in power-down.
The internal bandgap reference and its buffer generate
V_REFOUT to be 2.048V. The reference temperature coeffi-
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
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