MAX12555 Datasheet, PDF (16/28 Pages) Maxim Integrated Products – 14-Bit, 95Msps, 3.3V ADC

14-Bit, 95Msps, 3.3V ADC
All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor. Place the 1µF capacitor as close to
the device as possible on the same side of the PC
board. Bypass REFIN and REFOUT to GND with a
0.1µF capacitor.
For detailed circuit suggestions, see Figure 13 and
Figure 14.
Clock Input and Clock Control Lines
(CLKP, CLKN, CLKTYP)
The MAX12555 accepts both differential and single-
ended clock inputs. For single-ended clock input oper-
ation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock input operation, connect CLKTYP
to OV_DD or V_DD, and drive CLKP and CLKN with the
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.
CLKP and CLKN are high impedance when the
MAX12555 is powered down (Figure 5).
Low clock jitter is required for the specified SNR perfor-
mance of the MAX12555. Analog input sampling
occurs on the falling edge of the clock signal, requiring
this edge to have the lowest possible jitter. Jitter limits
the maximum SNR performance of any ADC according
to the following relationship:
⎛
SNR = 20 × log_⎜
1
⎞
⎟
⎝ 2 × π f_IN × t _J ⎠
where f_IN represents the analog input frequency and t_J
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 72.1dB of SNR with a 175MHz
input frequency, the system must have less than 0.23ps
of clock jitter. In actuality, there are other noise sources
such as thermal noise and quantization noise that con-
tribute to the system noise, requiring the clock jitter to
be less than 0.14ps to obtain the specified 72.1dB of
SNR at 175MHz.
V_DD
CLKP
CLKN
GND
S_1H
10kΩ
MAX12555
10kΩ
S_2H
S_1L
10kΩ
DUTY-CYCLE
EQUALIZER
10kΩ
SWITCHES S_{1_} AND S_{2_} ARE OPEN
DURING POWER-DOWN, MAKING
S_{2L CLKP AND CLKN HIGH IMPEDANCE.}
SWITCHES S_{2_} ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
Figure 5. Simplified Clock Input Circuit
Clock Duty-Cycle Equalizer (DCE)
Connect DCE high to enable the clock duty-cycle
equalizer (DCE = OV_DD or V_DD). Connect DCE low to
disable the clock duty-cycle equalizer (DCE = GND).
With the clock duty-cycle equalizer enabled, the
MAX12555 is insensitive to the duty cycle of the signal
applied to CLKP and CLKN. Duty cycles from 35% to
65% are acceptable with the clock duty-cycle equalizer
enabled.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12555 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Although not recommended, disabling the clock duty-
cycle equalizer reduces the analog supply current by
1.6mA. With the clock duty-cycle equalizer disabled, the
MAX12555’s dynamic performance varies depending on
the duty cycle of the signal applied to CLKP and CLKN.
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