MAX11047_11 Datasheet, PDF (18/25 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Bypass AVDD and DVDD to the ground plane with
0.1µF ceramic chip capacitors on each pin as close as
possible to the device to minimize parasitic inductance.
Add at least one bulk 10µF decoupling capacitor to
AVDD and DVDD per PCB. Interconnect all of the
AVDD inputs and DVDD inputs using two solid power
planes. For best performance, bring the AVDD power
plane in on the analog interface side of the devices and
the DVDD power plane from the digital interface side of
the devices.
For sampling periods near minimum (1µs) use a 1nF
C0G ceramic chip capacitor between each of the chan-
nel inputs to the ground plane as close as possible to the
devices. This capacitor reduces the inductance seen by
the sampling circuitry and reduces the voltage transient
seen by the input source circuit.
CS
(USER SUPPLIED)
WR
(USER SUPPLIED)
CR0–CR3
(USER SUPPLIED)
t₅
t₃
t₄
t₇
t₆
CONFIGURATION
REGISTER
Figure 4. Programming Configuration-Register Timing Requirements
CS
(USER SUPPLIED)
RD
(USER SUPPLIED)
DB0–DB15
t₈
t₉
t₁₀
t₁₁
t₁₂
t₁₃
S_n
S_{n + 1}
Figure 5. Readout Timing Requirements
18 ______________________________________________________________________________________