MAX11047_11 Datasheet, PDF (13/25 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
MAX11057 MAX11058 MAX11059
(TQFP-EP) (TQFP-EP) (TQFP-EP)
NAME
FUNCTION
1
2
3
4
5
6
7
8, 22, 59
9, 21, 60
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8, 22, 59
9, 21, 60
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8, 22, 59
9, 21, 60
10
11
12
13
14
15
16
17
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DGND
DV_DD
DB5
DB4
DB3
DB2
DB1/CR3
DB0/CR2
CR1
CR0
14-Bit Parallel Data Bus Digital Output Bit 12
14-Bit Parallel Data Bus Digital Output Bit 11
14-Bit Parallel Data Bus Digital Output Bit 10
14-Bit Parallel Data Bus Digital Output Bit 9
14-Bit Parallel Data Bus Digital Output Bit 8
14-Bit Parallel Data Bus Digital Output Bit 7
14-Bit Parallel Data Bus Digital Output Bit 6
Digital Ground
Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input.
14-Bit Parallel Data Bus Digital Output Bit 5
14-Bit Parallel Data Bus Digital Output Bit 4
14-Bit Parallel Data Bus Digital Output Bit 3
14-Bit Parallel Data Bus Digital Output Bit 2
14-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 3
14-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 2
Configuration Register Input Bit 1
Configuration Register Input Bit 0
18
18
18
EOC
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
Convert Start Input. The rising edge of CONVST ends sample and starts a
19
19
19
CONVST conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
20
20
20
SHDN low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
AGNDS Signal Ground. Connect all AGND and AGNDS inputs together.
24, 29, 35, 24, 29, 35, 24, 29, 35,
46, 52, 57 46, 52, 57 46, 52, 57
AV_DD
Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each
AVDD input.
25, 30, 36, 25, 30, 36, 25, 30, 36,
45, 51, 56 45, 51, 56 45, 51, 56
AGND Analog Ground. Connect all AGND inputs together.
26, 55
27, 33,
40,48, 54
26, 55
27, 33,
40,48, 54
26, 55
27, 33,
40,48, 54
RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane.
RDC
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
31, 34,
47, 50
31, 50
—
I.C.
Internally Connected. Connect to AGND.
37
34
31
CH0 Channel 0 Analog Input
39
37
34
CH1 Channel 1 Analog Input
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