MAX11047_11 Datasheet, PDF (12/25 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
MAX11047 MAX11048 MAX11049
(TQFP-EP) (TQFP-EP) (TQFP-EP)
NAME
FUNCTION
18
18
18
19
19
19
20
20
20
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
23, 28, 32,
38, 43, 49,
53, 58
EOC
CONVST
SHDN
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
Convert Start Input. The rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
AGNDS Signal Ground. Connect all AGND and AGNDS inputs together.
24, 29, 35, 24, 29, 35, 24, 29, 35,
46, 52, 57 46, 52, 57 46, 52, 57
AV_DD
Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each
AVDD input.
25, 30, 36,
45, 51, 56
26, 55
27, 33, 40,
48, 54
31, 34,
47, 50
37
39
41
42
44
—
—
—
—
25, 30, 36,
45, 51, 56
26, 55
27, 33, 40,
48, 54
31, 50
34
37
41
39
42
44
47
—
—
25, 30, 36,
45, 51, 56
AGND Analog Ground. Connect all AGND inputs together.
26, 55 RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane.
27, 33, 40,
48, 54
RDC
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
—
I.C.
Internally Connected. Connect to AGND.
31
CH0 Channel 0 Analog Input
34
CH1 Channel 1 Analog Input
41
REFIO
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
37
CH2 Channel 2 Analog Input
39
CH3 Channel 3 Analog Input
42
CH4 Channel 4 Analog Input
44
CH5 Channel 5 Analog Input
47
CH6 Channel 6 Analog Input
50
CH7 Channel 7 Analog Input
61
61
61
WR
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
62
62
62
CS
Active-Low Chip-Select Input. Drive CS low when reading from or writing to
the ADC.
63
63
63
RD
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
64
64
64
DB15 16-Bit Parallel Data Bus Digital Out Bit 15
Exposed Pad. Internally connected to AGND. Connect to a large ground
—
—
—
EP
plane to maximize thermal performance. Not intended as an electrical
connection point.
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