MAX11047_11 Datasheet, PDF (16/25 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
25
20
R_S = 1170I
V_AVDD = 5.0V
15
10 ^{AT CH_ INPUT}
5
0 _{AT SOURCE}
-5
-10
-15
-20
-25
-30 -20 -10 0 10 20 30 40
SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
Figure 2. Input Clamp Characteristics
Figures 2 and 3 illustrate the clamp circuit voltage-cur-
rent characteristics for a source impedance R_S =
1280Ω. While the input voltage is within the -300mV to
+(V_AVDD + 300mV) range, no current flows in the input
clamps. Once the input voltage goes beyond this volt-
age range, the clamps turn on and limit the voltage at
the input pin.
Applications Information
Digital Interface
The bidirectional, parallel, digital interface, CR0–CR3,
sets the 4-bit configuration register. This interface
configures the following control signals: chip select
(CS), read (RD), write (WR), end of conversion (EOC),
and convert start (CONVST). Figures 6 and 7 and the
Timing Characteristics in the Electrical Characteristics
table show the operation of the interface.
DB0–DB15/13, output the 16-/14-bit conversion result.
All bits are high impedance when RD = 1 or CS = 1.
CR3 (Int/Ext Reference)
CR3 selects the internal or external reference. The POR
default = 0.
0 = internal reference, REFIO internally driven through a
10kΩ resistor, bypass with 0.1µF capacitor to AGND.
1 = external reference, drive REFIO with a high quality
reference.
CR2 (Output Data Format)
CR2 selects the output data format. The POR default = 0.
0 = offset binary.
1 = two’s complement.
25
20
R_S = 1170I
V_AVDD = 5.0V
15
10
AT CH_ INPUT
5 ^{AT SOURCE}
0
-5
-10
-15
-20
-25
-4 -2 0 2 4 6 8
SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
Figure 3. Input Clamp Characteristics (Zoom In)
CR1 must be set to 0.
CR1 (Reserved)
CR0 (CONVST Mode)
CR0 selects the acquisition mode. The POR default = 0.
0 = CONVST controls the acquisition and conversion.
Drive CONVST low to start acquisition. The rising edge
of CONVST begins the conversion.
1 = acquisition mode starts as soon as previous con-
version is complete. The rising edge of CONVST begins
the conversion.
Programming the Configuration Register
To program the configuration register, bring the CS and
WR low and apply the required configuration data on
CR3–CR0 of the bus and then raise WR once to save
changes.
CAUTION: The host driving CR3–CR0 must relin-
quish the bus when the conversion results of the
ADC are being read.
Starting a Conversion
CONVST initiates conversions. The devices provide two
acquisition modes set through the configuration regis-
ter. Allow a quiet time (t_Q) of 500ns prior to the start of
conversion to avoid any noise interference during read-
out or write operations from corrupting a sample.
Table 1. Configuration Register
CR3
Int/Ext
Reference
CR2
Output
Data Format
CR1
Must be set
to 0
CR0
CONVST
Mode
16 ______________________________________________________________________________________