MAX1214N Datasheet, PDF (17/21 Pages) Maxim Integrated Products – 1.8V, Low-Power, 12-Bit, 210Msps ADC for Broadband Applications

1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Grounding, Bypassing, and
Board Layout Considerations
The MAX1214N requires board-layout design tech-
niques suitable for high-speed data converters. This
ADC provides separate analog and digital power sup-
plies. The analog and digital supply voltage pins
accept 1.7V to 1.9V input voltage ranges. Although
both supply types can be combined and supplied from
one source, it is recommended to use separate sources
to cut down on performance degradation caused by dig-
ital switching currents, which can couple into the analog
supply network. Isolate analog and digital supplies
(AV_CC and OV_CC) where they enter the PC board with
separate networks of ferrite beads and capacitors to
their corresponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor
and parallel combinations of 10µF and 1µF ceramic
capacitors. Additionally, the ADC requires each supply
pin to be bypassed with separate 0.1µF ceramic
capacitors (Figure 10). Locate these capacitors directly
at the ADC supply pins or as close as possible to the
MAX1214N. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. The dynamic currents that may need to travel
long distances before they are recombined at a com-
mon source ground, resulting in large and undesirable
ground loops, are a major concern with this approach.
Ground loops can degrade the input noise by coupling
back to the analog front-end of the converter, resulting
in increased spurious activity, leading to decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
coupling of the digital output signals from the analog
input, segregate the digital output bus carefully from the
analog input circuitry. To further minimize the effects of
digital noise coupling, ground return vias can be posi-
tioned throughout the layout to divert digital switching
currents away from the sensitive analog sections of the
ADC. This approach does not require split ground
planes, but can be accomplished by placing substantial
ground connections between the analog front-end and
the digital outputs.
The MAX1214N is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The exposed
paddle (EP) must be soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
BYPASSING—ADC LEVEL
AV_CC
OV_CC
BYPASSING—BOARD LEVEL
AV_CC
0.1µF
0.1µF
1µF
AGND
OGND
D0P/N–D11P/N, 0RP/N
MAX1214N
AGND
12
1µF
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
OGND
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
10µF
OV_CC
10µF
47µF
ANALOG POWER-
SUPPLY SOURCE
DIGITAL/OUTPUT
47µF _{DRIVER POWER-}
SUPPLY SOURCE
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1214N
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