DS1339A Datasheet, PDF (16/19 Pages) Maxim Integrated Products – Low-Current, I2C, Serial Real-Time Clock

DS1339A
Low-Current, I²C, Serial Real-Time Clock
Slave Address Byte: Each slave on the I²C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
whatever’s slave address is D0h and cannot be
modified by the user. When the R/W bit is 0 (such as in
D0h), the master is indicating it writes data to the slave.
If R/W = 1, (D1h in this case), the master is indicating
it wants to read from the slave. If an incorrect slave
address is written, the DS1339A assumes the master
is communicating with another I²C device and ignores
the communication until the next START condition is
sent.
Memory Address: During an I²C write operation, the
master must transmit a memory address to identify
the memory location where the slave is to store the
data. The memory address is always the second byte
transmitted during a write operation following the slave
address byte.
I²C Communication
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the byte
of data, and generate a STOP condition. Remember
the master must read the slave’s acknowledgment
during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START
condition, writes the slave address byte (R/W = 0),
writes the starting memory address, writes multiple
data bytes, and generates a STOP condition.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, since requiring
the master to keep track of the memory address
counter is impractical, the following method should
be used to perform reads from a specified memory
location.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master
TYPICAL I²C WRITE TRANSACTION
MSB
LSB
MSB
LSB
MSB
LSB
START
1
1
0
1
0
0
0
R/W
SLAVE
ACK
b7
b6
b5
b4
b3
b2
b1
b0
SLAVE
ACK
b7 b6 b5 b4 b3 b2 b1 b0
SLAVE
ACK
STOP
SLAVE
READ/
REGISTER ADDRESS
DATA
ADDRESS
WRITE
EXAMPLE I²C TRANSACTIONS
A) SINGLE BYTE WRITE
-WRITE CONTROL REGISTER
TO B8h
B) SINGLE BYTE READ
-READ CONTROL REGISTER
D0h
0Eh
B8h
START
11010000
SLAVE
ACK
00001110
SLAVE
ACK
10111000
SLAVE
ACK
STOP
D0h
0Eh
START
11010000
SLAVE
ACK
00001110
SLAVE
ACK
REPEATED
START
D1h
11010001
SLAVE
ACK
DATA
VALUE
MASTER
NACK
STOP
C) MULTIBYTE WRITE
-WRITE DATE REGISTER TO "02"
AND MONTH REGISTER TO "11"
D) MULTIBYTE READ
-READ HOURS AND DAY
REGISTER VALUES
D0h
04h
02h
START
11010000
SLAVE
ACK
00000100
SLAVE
ACK
00000010
SLAVE
ACK
11h
00010001
SLAVE
ACK
STOP
D0h
02h
START
11010000
SLAVE
ACK
00000010
SLAVE
ACK
REPEATED
START
D1h
11010001
SLAVE
ACK
DATA
VALUE
MASTER
ACK
Figure 5. I²C Transactions
DATA
VALUE
MASTER
NACK
STOP
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