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DS1339A Datasheet, PDF (12/19 Pages) Maxim Integrated Products – Low-Current, I2C, Serial Real-Time Clock
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DS1339A
Low-Current, I2C, Serial Real-Time Clock
Control Register (0Eh)
The control register controls the operation of the SQW/INT pin and provides oscillator status.
Bit #
Name
POR
BIT 7
EOSC
0
BIT 6
0
0
BIT 5
BBSQI
0
BIT 4
RS2
1
BIT 3
RS1
1
BIT 2
INTCN
0
BIT 1
A2IE
0
BIT 0
A1IE
0
Bit 7: Enable Oscillator (EOSC). When the EOSC bit is 0, the oscillator is enabled. When this bit is a 1, the oscillator
is disabled. This bit is cleared (0) when power is first applied.
Bit 5: Battery-Backed Square-Wave Interrupt (BBSQI). When set to logic 1, this bit enables the SQW/INT output
functionality while the part is powered by VBACKUP. When set to logic 0, this bit disables the SQW/INT output while the
part is powered by VBACKUP.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the SQW/INT output when the square-
wave has been enabled (INTCN=0). Table 5 lists the square-wave frequencies that can be selected with the RS bits.
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pin.
When the INTCN bit is set to logic 1, a match between the timekeeping registers and the Alarm 1 or Alarm 2 registers
activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a square wave is
output on the SQW/INT pin. This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the status
register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit
does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status
register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit
does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
Table 5. SQW/INT Output
INTCN
RS2
RS1
0
0
0
0
0
1
0
1
0
0
1
1
1
X
X
1
X
X
1
X
X
SQW/INT OUTPUT
1Hz
4.096kHz
8.192kHz
32.768kHz
A1F
A2F
A2F + A1F
A2IE
X
X
X
X
0
1
1
A1IE
X
X
X
X
1
0
1
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