MAX1586A_08 Datasheet, PDF (15/30 Pages) Maxim Integrated Products – High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones

High-Efficiency, Low-I_Q PMICs with
Dynamic Core for PDAs and Smart Phones
Pin Description (continued)
PIN
MAX MAX
1586 1587
NAME
FUNCTION
16
13 PV2 ^{REG2 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR capacitor. PV1, PV2, PV3, and IN must}
connect together externally.
17 14 LX2 REG2 Switching Node. Connects to REG2 inductor.
18
15
PG2
REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.
19 16
IN Main Battery Input. This input provides power to the IC.
20
17
RAMP
V3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is
changed. The output impedance of RAMP is 100kΩ. FB3 regulates to 1.28 x V_RAMP.
21 18 GND Analog Ground
22 19 REF Reference Output. Output of the 1.25V reference. Bypass to GND with a 0.1µF or greater capacitor.
23 20 BYP Low-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01µF capacitor from BYP to GND.
Dead or Missing Battery Output. DBO is an open-drain output that goes low when IN is below the threshold
24 — DBO set by DBI. DBO does not deactivate any MAX1586/MAX1587 regulator outputs. DBO is expected to
connect to nBATT_FAULT on Intel CPUs.
On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has
25 21 ON2 hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 are connected to SYS_EN.
On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis
26 — ON4 so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that
ON4 is connected to PWR_EN.
27 23 V4 Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45.
28
24 IN45 ^{Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage}
from 2.5V to V_IN.
29 25 V5 Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45.
On/Off Input for REG5. Drive high to turn on. When enabled, the MAX1586/MAX1587 soft-starts the REG5
30 — ON5 output. ON5 has hysteresis so an RC can be used to implement manual sequencing with respect to other
inputs. It is expected that ON5 is connected to PWR_EN.
31
26
PG3
REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.
32 27 LX3 REG3 Switching Node. Connects to the REG3 inductor.
33
28
PV3
REG3 Power Input. Bypass to PG3 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and
IN must connect together externally.
On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has
34 34 ON3 hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON3 is driven from CPU SYS_EN.
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