DS1347_13 Datasheet, PDF (15/17 Pages) Maxim Integrated Products – Low-Current, SPI-Compatible Real-Time Clock

DS1347
Low-Current, SPI-Compatible
Real-Time Clock
Chip Select
CS serves two functions. First, CS turns on the control
logic that allows access to the Shift register for
address/command and data transfer. Second, CS pro-
vides a method of terminating either single-byte or mul-
tiple-byte data transfers. All data transfers are initiated
by driving CS low. If CS is high, then DOUT is high
impedance.
Serial Clock
A clock cycle on SCLK is a rising edge followed by a
falling edge. For data input, data must be valid at DIN
before the rising edge of the clock. For data outputs, bits
are valid on DOUT after the falling edge of the clock.
Data Input (Single-Byte Write)
Following the eight SCLK cycles that input a single-byte
write address/command, data bits are input on the ris-
ing edges of the next eight SCLK cycles. Additional
SCLK cycles are ignored. Input data MSB first.
Data Input (Burst Write)
Following the eight SCLK cycles that input a burst-write
address/command, data bits are input on the rising
edges of the following SCLK cycles. The number of
clock cycles depends on whether the timekeeping reg-
isters or RAM are being written. A clock burst write
requires 1 address/command byte, 7 timekeeping data
bytes, and 1 control register byte. A burst write to RAM
can be terminated after any complete data byte by dri-
ving CS high. Input data MSB first (Figure 1).
Data Output (Single-Byte Read
and Burst Read)
A read from the device is initiated by an address/com-
mand Write from the microcontroller (master) to the
device (slave). The address/command write portion of
the data transfer is clocked into the device on rising
clock edges. Following the eighth falling clock edge of
SCLK, after t_DO (Figure 2) data begins to be output on
DOUT of the device. Data bytes are output MSB first.
Additional SCLK cycles transmit additional data bits, as
long as CS remains low. This permits continuous burst-
mode read capability.
Applications Information
Oscillator Start Time
The device’s oscillator typically takes less than 2s to
begin oscillating. To ensure the oscillator is operating
correctly, the software should validate proper time-
keeping. This is accomplished by reading the Seconds
register. Any reading of 1s or more from the POR value
of zero seconds is a validation of proper startup.
Power-On Reset
The device contains an integral POR circuit that
ensures all registers are reset to a known state on
power-up. Upon a POR, the time and date are set to
00:00:00 01/01/1970 (hh:mm:ss DD/MM/YYYY) and the
day register is set to 01. Once V_CC rises, the POR cir-
cuit releases the registers for normal operation.
Power-Supply Considerations
For most applications, a 0.1µF capacitor from V_CC to
GND provides adequate bypassing for the device. A
series resistor can be added to the supply line for oper-
ation in extremely harsh or noisy environments.
PCB Considerations
The device uses a very low-current oscillator to mini-
mize supply current. This causes the oscillator pins, X1
and X2, to be relatively high impedance. Exercise care
to prevent unwanted noise pickup.
Connect the 32.768kHz crystal directly across X1 and X2
of the device. To eliminate unwanted noise pickup,
design the PCB using these guidelines (Figure 4):
1) Place the crystal as close to X1 and X2 as possible
and keep the trace lengths short.
2) Place a guard ring around the crystal, X1 and X2
traces (where applicable), and connect the guard
ring to GND; keep all signal traces away from
beneath the crystal, X1, and X2.
3) Finally, an additional local ground plane can be
added under the crystal on an adjacent PCB layer.
The plane should be isolated from the regular PCB
ground plane, and connected to ground at the IC
ground pin.
4) Restrict the plane to be no larger than the perimeter of
the guard ring. Do not allow this ground plane to con-
tribute significant capacitance between X1 and X2.
Maxim Integrated
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