DS1347_13 Datasheet, PDF (13/17 Pages) Maxim Integrated Products – Low-Current, SPI-Compatible Real-Time Clock

DS1347
Low-Current, SPI-Compatible
Real-Time Clock
microcontroller, is active only during address and data
transfer to any device on the SPI bus. The inactive clock
polarity is usually programmable on the microcontroller
side of the SPI interface. In the device, input data is
latched on the positive edge, and output data is shifted
out on the negative edge. There is one clock cycle for
each bit transferred. Address and data bits are trans-
ferred in groups of eight.
The SPI protocol allows for one of four combinations of
serial clock phase and polarity from the microcontroller,
through a 2-bit selection in its SPI Control register. The
clock polarity is specified by the CPOL Control bit,
which selects active-high or active-low clock, and has
no significant effect on the transfer format. The clock
phase control bit, CPHA, selects one of two different
transfer formats. The clock phase and polarity must be
identical for the master and the slave. For the device,
set the control bits to CPHA = 1 and CPOL = 1. This
configures the system for data out to be launched on
the negative edge of SCLK and data in to be sampled
on the positive edge. With CPHA equal to 1, CS can
remain low between successive data byte transfers,
allowing burst-mode data transfers to occur.
Address and data bytes are shifted MSB first into DIN
of the device, and out of DOUT. Data is shifted out at
the negative edge of SCLK, and shifted in or sampled
at the positive edge of SCLK. Any transfer requires an
address/command byte followed by one or more
bytes of data. Data is transferred out of DOUT for a
read operation, and into DIN for a write operation.
DOUT transmits data only after an address/command
byte specifies a read operation; otherwise, it is high
impedance.
Data transfer write timing is shown in Figure 1. Data
transfer read timing is shown in Figure 2. Detailed read
and write timing is shown in Figure 3.
CS
SCLK
DIN
R/W A6 A5 A4 A3 A2 A1 1
ADDRESS/COMMAND BYTE
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
DOUT
HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.
Figure 1a. Single Write
CS
SCLK
DIN
R/W A6 1 1 1 1 1 1
ADDRESS/COMMAND BYTE*
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE 1
DOUT
HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.
*ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.
Figure 2b. Burst Write
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE N
Maxim Integrated
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