MAX15109 Datasheet, PDF (14/19 Pages) Maxim Integrated Products – High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator

High-Efficiency, 8A, Current-Mode Synchronous
Step-Down Switching Regulator with VID Control
Compensation Design Guidelines
The IC uses a fixed-frequency, peak-current-mode con-
trol scheme to provide easy compensation and fast tran-
sient response. The inductor peak current is monitored
on a cycle-by-cycle basis and compared to the COMP
voltage (output of the voltage error amplifier). The regu-
lator’s duty cycle is modulated based on the inductor’s
peak current value. This cycle-by-cycle control of the
inductor current emulates a controlled current source.
As a result, the inductor’s pole frequency is shifted
beyond the gain bandwidth of the regulator. System
stability is provided with the addition of a simple series
capacitor-resistor from COMP to PGND. This pole-zero
combination serves to tailor the desired response of the
closed-loop system. The basic regulator loop consists
of a power modulator (comprising the regulator’s pulse-
width modulator, compensation ramp, control circuitry,
MOSFETs, and inductor), the capacitive output filter
and load, an output feedback, and a voltage-loop error
amplifier with its associated compensation circuitry. See
Figure 1.
The average current through the inductor is expressed
as:
I_L = G_MOD × V_COMP
where IL is the average inductor current and GMOD is
the power modulator’s transconductance.
For a buck converter:
V_OUT = R_LOAD × I_L
where RLOAD is the equivalent load resistor value.
Combining the above two relationships, the power mod-
ulator’s transfer function in terms of VOUT with respect
to VCOMP is:
V_FB
V_COMP
=
R_LOAD × I_L
I_L
= R_LOAD × G_MOD
G_MOD
Having defined the power modulator’s transfer function
gain, the total system loop gain can be written as follows
(see Figure 1):
α
=
R_OUT × (sC_CR_C + 1)
s₍C_C + C_CC)(R_C + R_OUT)
+ 1
×
s₍C_C || C_CC)(R_C || R_OUT) + 1
β
=
G_MOD
×
R_LOAD
×
(sC_OUTESR + 1)
sC_{OUT (}ESR + R_LOAD)
+
1
Gain = ^R2 × ^{A VEA} × α × β
R₁ + R₂ R_OUT
where ROUT is the quotient of the error amplifier’s DC
gain, AVEA, divided by the error amplifier’s transconduc-
tance, gMV; ROUT is much larger than RC.
R_{2 =} V_FB
R₁ + R₂ V_OUT
Also, CC is much larger than CCC, therefore:
C_C + C_CC ≈ C_C
and
Rewriting:
C_C || C_CC ≈ C_CC
Gain
=
V_FB
V_OUT
A
VEA
×

^sC _C 
 
(sC_CR_C + 1)
A _VEA
g_MV



+

1_

×
(sC
CC^R
C
+
1)
×
G_MOD
R_LOAD
×
(sC_OUTESR + 1)
sC_{OUT (}ESR + R_LOAD)
+
1
The dominant poles and zeros of the transfer loop gain
are shown below:
f_P1
=
2π
× 10
g_MV
AVEA _dB/ 20
×
C_C
f_P2
=
2π
×
1
C_OUT (ESR
+
R_LOAD)
f_P3
=
2π
×
1
C _CCR _C
f_Z1
=
2π
×
1
C _CR _C
f_Z2
=
2π
×
1
C_OUTESR
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